clk: mmp: add pxa910 DT support for clock driver
It adds the DT support for pxa910 clock subsystem. Signed-off-by: Chao Xie <chao.xie@marvell.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
This commit is contained in:
Chao Xie
Michael Turquette
parent
ab08aefcd1
commit
2bc61da9f7
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@ -0,0 +1,21 @@
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* Marvell PXA910 Clock Controller
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The PXA910 clock subsystem generates and supplies clock to various
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controllers within the PXA910 SoC.
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Required Properties:
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- compatible: should be one of the following.
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- "marvell,pxa910-clock" - controller compatible with PXA910 SoC.
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- reg: physical base address of the clock subsystem and length of memory mapped
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region. There are 4 places in SOC has clock control logic:
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"mpmu", "apmu", "apbc", "apbcp". So four reg spaces need to be defined.
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- #clock-cells: should be 1.
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- #reset-cells: should be 1.
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Each clock is assigned an identifier and client nodes use this identifier
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to specify the clock which they consume.
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All these identifier could be found in <dt-bindings/clock/marvell-pxa910.h>.
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@ -6,7 +6,7 @@ obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o clk-gate.o clk.o
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obj-$(CONFIG_RESET_CONTROLLER) += reset.o
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obj-$(CONFIG_MACH_MMP_DT) += clk-of-pxa168.o
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obj-$(CONFIG_MACH_MMP_DT) += clk-of-pxa168.o clk-of-pxa910.o
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obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
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obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
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@ -0,0 +1,301 @@
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/*
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* pxa910 clock framework source file
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*
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* Copyright (C) 2012 Marvell
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* Chao Xie <xiechao.mail@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/of_address.h>
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#include <dt-bindings/clock/marvell,pxa910.h>
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#include "clk.h"
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#include "reset.h"
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#define APBC_RTC 0x28
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#define APBC_TWSI0 0x2c
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#define APBC_KPC 0x18
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#define APBC_UART0 0x0
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#define APBC_UART1 0x4
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#define APBC_GPIO 0x8
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#define APBC_PWM0 0xc
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#define APBC_PWM1 0x10
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#define APBC_PWM2 0x14
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#define APBC_PWM3 0x18
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#define APBC_SSP0 0x1c
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#define APBC_SSP1 0x20
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#define APBC_SSP2 0x4c
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#define APBCP_TWSI1 0x28
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#define APBCP_UART2 0x1c
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#define APMU_SDH0 0x54
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#define APMU_SDH1 0x58
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#define APMU_USB 0x5c
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#define APMU_DISP0 0x4c
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#define APMU_CCIC0 0x50
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#define APMU_DFC 0x60
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#define MPMU_UART_PLL 0x14
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struct pxa910_clk_unit {
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struct mmp_clk_unit unit;
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void __iomem *mpmu_base;
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void __iomem *apmu_base;
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void __iomem *apbc_base;
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void __iomem *apbcp_base;
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};
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static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
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{PXA910_CLK_CLK32, "clk32", NULL, CLK_IS_ROOT, 32768},
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{PXA910_CLK_VCTCXO, "vctcxo", NULL, CLK_IS_ROOT, 26000000},
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{PXA910_CLK_PLL1, "pll1", NULL, CLK_IS_ROOT, 624000000},
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};
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static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
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{PXA910_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
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{PXA910_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
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{PXA910_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
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{PXA910_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
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{PXA910_CLK_PLL1_6, "pll1_6", "pll1_2", 1, 3, 0},
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{PXA910_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
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{PXA910_CLK_PLL1_24, "pll1_24", "pll1_12", 1, 2, 0},
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{PXA910_CLK_PLL1_48, "pll1_48", "pll1_24", 1, 2, 0},
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{PXA910_CLK_PLL1_96, "pll1_96", "pll1_48", 1, 2, 0},
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{PXA910_CLK_PLL1_13, "pll1_13", "pll1", 1, 13, 0},
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{PXA910_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 2, 3, 0},
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{PXA910_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 2, 3, 0},
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{PXA910_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
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};
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static struct mmp_clk_factor_masks uart_factor_masks = {
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.factor = 2,
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.num_mask = 0x1fff,
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.den_mask = 0x1fff,
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.num_shift = 16,
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.den_shift = 0,
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};
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static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
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{.num = 8125, .den = 1536}, /*14.745MHZ */
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};
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static void pxa910_pll_init(struct pxa910_clk_unit *pxa_unit)
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{
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struct clk *clk;
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struct mmp_clk_unit *unit = &pxa_unit->unit;
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mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
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ARRAY_SIZE(fixed_rate_clks));
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mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
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ARRAY_SIZE(fixed_factor_clks));
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clk = mmp_clk_register_factor("uart_pll", "pll1_4",
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CLK_SET_RATE_PARENT,
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pxa_unit->mpmu_base + MPMU_UART_PLL,
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&uart_factor_masks, uart_factor_tbl,
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ARRAY_SIZE(uart_factor_tbl), NULL);
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mmp_clk_add(unit, PXA910_CLK_UART_PLL, clk);
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}
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static DEFINE_SPINLOCK(uart0_lock);
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static DEFINE_SPINLOCK(uart1_lock);
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static DEFINE_SPINLOCK(uart2_lock);
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static const char *uart_parent_names[] = {"pll1_3_16", "uart_pll"};
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static DEFINE_SPINLOCK(ssp0_lock);
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static DEFINE_SPINLOCK(ssp1_lock);
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static const char *ssp_parent_names[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
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static DEFINE_SPINLOCK(reset_lock);
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static struct mmp_param_mux_clk apbc_mux_clks[] = {
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{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
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{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
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{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
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{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
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};
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static struct mmp_param_mux_clk apbcp_mux_clks[] = {
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{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBCP_UART2, 4, 3, 0, &uart2_lock},
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};
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static struct mmp_param_gate_clk apbc_gate_clks[] = {
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{PXA910_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &reset_lock},
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{PXA910_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_lock},
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{PXA910_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x3, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
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{PXA910_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x83, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
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{PXA910_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_lock},
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{PXA910_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_lock},
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{PXA910_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &reset_lock},
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{PXA910_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_lock},
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/* The gate clocks has mux parent. */
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{PXA910_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &uart0_lock},
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{PXA910_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 0x3, 0x0, 0, &uart1_lock},
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{PXA910_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_lock},
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{PXA910_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_lock},
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};
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static struct mmp_param_gate_clk apbcp_gate_clks[] = {
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{PXA910_CLK_TWSI1, "twsi1_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBCP_TWSI1, 0x3, 0x3, 0x0, 0, &reset_lock},
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/* The gate clocks has mux parent. */
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{PXA910_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBCP_UART2, 0x3, 0x3, 0x0, 0, &uart2_lock},
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};
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static void pxa910_apb_periph_clk_init(struct pxa910_clk_unit *pxa_unit)
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{
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struct mmp_clk_unit *unit = &pxa_unit->unit;
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mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
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ARRAY_SIZE(apbc_mux_clks));
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mmp_register_mux_clks(unit, apbcp_mux_clks, pxa_unit->apbcp_base,
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ARRAY_SIZE(apbcp_mux_clks));
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mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
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ARRAY_SIZE(apbc_gate_clks));
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mmp_register_gate_clks(unit, apbcp_gate_clks, pxa_unit->apbcp_base,
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ARRAY_SIZE(apbcp_gate_clks));
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}
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static DEFINE_SPINLOCK(sdh0_lock);
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static DEFINE_SPINLOCK(sdh1_lock);
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static const char *sdh_parent_names[] = {"pll1_12", "pll1_13"};
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static DEFINE_SPINLOCK(usb_lock);
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static DEFINE_SPINLOCK(disp0_lock);
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static const char *disp_parent_names[] = {"pll1_2", "pll1_12"};
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static DEFINE_SPINLOCK(ccic0_lock);
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static const char *ccic_parent_names[] = {"pll1_2", "pll1_12"};
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static const char *ccic_phy_parent_names[] = {"pll1_6", "pll1_12"};
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static struct mmp_param_mux_clk apmu_mux_clks[] = {
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{0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6, 1, 0, &sdh0_lock},
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{0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6, 1, 0, &sdh1_lock},
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{0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 1, 0, &disp0_lock},
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{0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 6, 1, 0, &ccic0_lock},
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{0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock},
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};
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static struct mmp_param_div_clk apmu_div_clks[] = {
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{0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
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};
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static struct mmp_param_gate_clk apmu_gate_clks[] = {
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{PXA910_CLK_DFC, "dfc_clk", "pll1_4", CLK_SET_RATE_PARENT, APMU_DFC, 0x19b, 0x19b, 0x0, 0, NULL},
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{PXA910_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
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{PXA910_CLK_SPH, "sph_clk", "usb_pll", 0, APMU_USB, 0x12, 0x12, 0x0, 0, &usb_lock},
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/* The gate clocks has mux parent. */
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{PXA910_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh0_lock},
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{PXA910_CLK_SDH1, "sdh1_clk", "sdh1_mux", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh1_lock},
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{PXA910_CLK_DISP0, "disp0_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},
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{PXA910_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
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{PXA910_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
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{PXA910_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},
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};
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static void pxa910_axi_periph_clk_init(struct pxa910_clk_unit *pxa_unit)
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{
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struct mmp_clk_unit *unit = &pxa_unit->unit;
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mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,
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ARRAY_SIZE(apmu_mux_clks));
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mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,
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ARRAY_SIZE(apmu_div_clks));
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mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
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ARRAY_SIZE(apmu_gate_clks));
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}
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static void pxa910_clk_reset_init(struct device_node *np,
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struct pxa910_clk_unit *pxa_unit)
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{
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struct mmp_clk_reset_cell *cells;
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int i, base, nr_resets_apbc, nr_resets_apbcp, nr_resets;
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nr_resets_apbc = ARRAY_SIZE(apbc_gate_clks);
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nr_resets_apbcp = ARRAY_SIZE(apbcp_gate_clks);
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nr_resets = nr_resets_apbc + nr_resets_apbcp;
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cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL);
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if (!cells)
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return;
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base = 0;
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for (i = 0; i < nr_resets_apbc; i++) {
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cells[base + i].clk_id = apbc_gate_clks[i].id;
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cells[base + i].reg =
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pxa_unit->apbc_base + apbc_gate_clks[i].offset;
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cells[base + i].flags = 0;
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cells[base + i].lock = apbc_gate_clks[i].lock;
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cells[base + i].bits = 0x4;
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}
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base = nr_resets_apbc;
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for (i = 0; i < nr_resets_apbcp; i++) {
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cells[base + i].clk_id = apbcp_gate_clks[i].id;
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cells[base + i].reg =
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pxa_unit->apbc_base + apbc_gate_clks[i].offset;
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cells[base + i].flags = 0;
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cells[base + i].lock = apbc_gate_clks[i].lock;
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cells[base + i].bits = 0x4;
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}
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mmp_clk_reset_register(np, cells, nr_resets);
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}
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static void __init pxa910_clk_init(struct device_node *np)
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{
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struct pxa910_clk_unit *pxa_unit;
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pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
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if (!pxa_unit)
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return;
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pxa_unit->mpmu_base = of_iomap(np, 0);
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if (!pxa_unit->mpmu_base) {
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pr_err("failed to map mpmu registers\n");
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return;
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}
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pxa_unit->apmu_base = of_iomap(np, 1);
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if (!pxa_unit->mpmu_base) {
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pr_err("failed to map apmu registers\n");
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return;
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}
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pxa_unit->apbc_base = of_iomap(np, 2);
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if (!pxa_unit->apbc_base) {
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pr_err("failed to map apbc registers\n");
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return;
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}
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pxa_unit->apbcp_base = of_iomap(np, 3);
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if (!pxa_unit->mpmu_base) {
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pr_err("failed to map apbcp registers\n");
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return;
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}
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||||
|
||||
mmp_clk_init(np, &pxa_unit->unit, PXA910_NR_CLKS);
|
||||
|
||||
pxa910_pll_init(pxa_unit);
|
||||
|
||||
pxa910_apb_periph_clk_init(pxa_unit);
|
||||
|
||||
pxa910_axi_periph_clk_init(pxa_unit);
|
||||
|
||||
pxa910_clk_reset_init(np, pxa_unit);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(pxa910_clk, "marvell,pxa910-clock", pxa910_clk_init);
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
#ifndef __DTS_MARVELL_PXA910_CLOCK_H
|
||||
#define __DTS_MARVELL_PXA910_CLOCK_H
|
||||
|
||||
/* fixed clocks and plls */
|
||||
#define PXA910_CLK_CLK32 1
|
||||
#define PXA910_CLK_VCTCXO 2
|
||||
#define PXA910_CLK_PLL1 3
|
||||
#define PXA910_CLK_PLL1_2 8
|
||||
#define PXA910_CLK_PLL1_4 9
|
||||
#define PXA910_CLK_PLL1_8 10
|
||||
#define PXA910_CLK_PLL1_16 11
|
||||
#define PXA910_CLK_PLL1_6 12
|
||||
#define PXA910_CLK_PLL1_12 13
|
||||
#define PXA910_CLK_PLL1_24 14
|
||||
#define PXA910_CLK_PLL1_48 15
|
||||
#define PXA910_CLK_PLL1_96 16
|
||||
#define PXA910_CLK_PLL1_13 17
|
||||
#define PXA910_CLK_PLL1_13_1_5 18
|
||||
#define PXA910_CLK_PLL1_2_1_5 19
|
||||
#define PXA910_CLK_PLL1_3_16 20
|
||||
#define PXA910_CLK_UART_PLL 27
|
||||
|
||||
/* apb periphrals */
|
||||
#define PXA910_CLK_TWSI0 60
|
||||
#define PXA910_CLK_TWSI1 61
|
||||
#define PXA910_CLK_TWSI2 62
|
||||
#define PXA910_CLK_TWSI3 63
|
||||
#define PXA910_CLK_GPIO 64
|
||||
#define PXA910_CLK_KPC 65
|
||||
#define PXA910_CLK_RTC 66
|
||||
#define PXA910_CLK_PWM0 67
|
||||
#define PXA910_CLK_PWM1 68
|
||||
#define PXA910_CLK_PWM2 69
|
||||
#define PXA910_CLK_PWM3 70
|
||||
#define PXA910_CLK_UART0 71
|
||||
#define PXA910_CLK_UART1 72
|
||||
#define PXA910_CLK_UART2 73
|
||||
#define PXA910_CLK_SSP0 74
|
||||
#define PXA910_CLK_SSP1 75
|
||||
|
||||
/* axi periphrals */
|
||||
#define PXA910_CLK_DFC 100
|
||||
#define PXA910_CLK_SDH0 101
|
||||
#define PXA910_CLK_SDH1 102
|
||||
#define PXA910_CLK_SDH2 103
|
||||
#define PXA910_CLK_USB 104
|
||||
#define PXA910_CLK_SPH 105
|
||||
#define PXA910_CLK_DISP0 106
|
||||
#define PXA910_CLK_CCIC0 107
|
||||
#define PXA910_CLK_CCIC0_PHY 108
|
||||
#define PXA910_CLK_CCIC0_SPHY 109
|
||||
|
||||
#define PXA910_NR_CLKS 200
|
||||
#endif
|
||||
Loading…
Reference in New Issue