drm/amd/powerplay: add the hw manager for vega12 (v4)
handles the driver power state setup v2: squash in the following: - handle negative temperature ranges - add vega12 thermal ranges - use ffs/fls - remove ACG code - resend NumOfDisplays message - correct max dpm levels - remove power containment settings - fix warnings - add sensors interface - delete unused overdrive arbiter - drop get_temperature callback - smu table cleanup - atomfirmware smu dpm table updates v3: rebase v4: rebase Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan
Alex Deucher
parent
fa969db4ad
commit
2cac05dee6
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@ -23,7 +23,7 @@
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#ifndef _DM_PP_INTERFACE_
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#define _DM_PP_INTERFACE_
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#define PP_MAX_CLOCK_LEVELS 8
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#define PP_MAX_CLOCK_LEVELS 16
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enum amd_pp_display_config_type{
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AMD_PP_DisplayConfigType_None = 0,
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@ -31,7 +31,9 @@ HARDWARE_MGR = hwmgr.o processpptables.o \
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smu7_clockpowergating.o \
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vega10_processpptables.o vega10_hwmgr.o vega10_powertune.o \
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vega10_thermal.o smu10_hwmgr.o pp_psm.o\
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pp_overdriver.o smu_helper.o pp_psm_legacy.o pp_psm_new.o
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pp_overdriver.o smu_helper.o pp_psm_legacy.o pp_psm_new.o \
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vega12_processpptables.o vega12_hwmgr.o \
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vega12_powertune.o vega12_thermal.o
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AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
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@ -41,11 +41,13 @@ extern const struct pp_smumgr_func tonga_smu_funcs;
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extern const struct pp_smumgr_func fiji_smu_funcs;
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extern const struct pp_smumgr_func polaris10_smu_funcs;
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extern const struct pp_smumgr_func vega10_smu_funcs;
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extern const struct pp_smumgr_func vega12_smu_funcs;
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extern const struct pp_smumgr_func smu10_smu_funcs;
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extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
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extern int smu8_init_function_pointers(struct pp_hwmgr *hwmgr);
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extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
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extern int vega12_hwmgr_init(struct pp_hwmgr *hwmgr);
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extern int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);
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static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);
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@ -186,6 +188,10 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
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hwmgr->smumgr_funcs = &vega10_smu_funcs;
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vega10_hwmgr_init(hwmgr);
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break;
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case CHIP_VEGA12:
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hwmgr->smumgr_funcs = &vega12_smu_funcs;
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vega12_hwmgr_init(hwmgr);
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break;
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default:
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return -EINVAL;
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}
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,470 @@
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/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _VEGA12_HWMGR_H_
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#define _VEGA12_HWMGR_H_
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#include "hwmgr.h"
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#include "vega12/smu9_driver_if.h"
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#include "ppatomfwctrl.h"
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#define VEGA12_MAX_HARDWARE_POWERLEVELS 2
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#define WaterMarksExist 1
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#define WaterMarksLoaded 2
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#define VG12_PSUEDO_NUM_GFXCLK_DPM_LEVELS 8
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#define VG12_PSUEDO_NUM_SOCCLK_DPM_LEVELS 8
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#define VG12_PSUEDO_NUM_DCEFCLK_DPM_LEVELS 8
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#define VG12_PSUEDO_NUM_UCLK_DPM_LEVELS 4
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enum
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{
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GNLD_DPM_PREFETCHER = 0,
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GNLD_DPM_GFXCLK,
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GNLD_DPM_UCLK,
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GNLD_DPM_SOCCLK,
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GNLD_DPM_UVD,
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GNLD_DPM_VCE,
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GNLD_ULV,
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GNLD_DPM_MP0CLK,
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GNLD_DPM_LINK,
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GNLD_DPM_DCEFCLK,
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GNLD_DS_GFXCLK,
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GNLD_DS_SOCCLK,
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GNLD_DS_LCLK,
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GNLD_PPT,
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GNLD_TDC,
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GNLD_THERMAL,
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GNLD_GFX_PER_CU_CG,
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GNLD_RM,
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GNLD_DS_DCEFCLK,
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GNLD_ACDC,
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GNLD_VR0HOT,
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GNLD_VR1HOT,
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GNLD_FW_CTF,
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GNLD_LED_DISPLAY,
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GNLD_FAN_CONTROL,
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GNLD_DIDT,
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GNLD_GFXOFF,
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GNLD_CG,
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GNLD_ACG,
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GNLD_FEATURES_MAX
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};
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#define GNLD_DPM_MAX (GNLD_DPM_DCEFCLK + 1)
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#define SMC_DPM_FEATURES 0x30F
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struct smu_features {
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bool supported;
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bool enabled;
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bool allowed;
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uint32_t smu_feature_id;
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uint64_t smu_feature_bitmap;
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};
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struct vega12_performance_level {
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uint32_t soc_clock;
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uint32_t gfx_clock;
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uint32_t mem_clock;
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};
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struct vega12_bacos {
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uint32_t baco_flags;
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/* struct vega12_performance_level performance_level; */
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};
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struct vega12_uvd_clocks {
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uint32_t vclk;
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uint32_t dclk;
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};
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struct vega12_vce_clocks {
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uint32_t evclk;
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uint32_t ecclk;
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};
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struct vega12_power_state {
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uint32_t magic;
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struct vega12_uvd_clocks uvd_clks;
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struct vega12_vce_clocks vce_clks;
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uint16_t performance_level_count;
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bool dc_compatible;
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uint32_t sclk_threshold;
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struct vega12_performance_level performance_levels[VEGA12_MAX_HARDWARE_POWERLEVELS];
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};
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struct vega12_dpm_level {
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bool enabled;
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uint32_t value;
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uint32_t param1;
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};
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#define VEGA12_MAX_DEEPSLEEP_DIVIDER_ID 5
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#define MAX_REGULAR_DPM_NUMBER 8
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#define MAX_PCIE_CONF 2
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#define VEGA12_MINIMUM_ENGINE_CLOCK 2500
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struct vega12_dpm_state {
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uint32_t soft_min_level;
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uint32_t soft_max_level;
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uint32_t hard_min_level;
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uint32_t hard_max_level;
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};
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struct vega12_single_dpm_table {
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uint32_t count;
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struct vega12_dpm_state dpm_state;
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struct vega12_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
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};
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struct vega12_odn_dpm_control {
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uint32_t count;
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uint32_t entries[MAX_REGULAR_DPM_NUMBER];
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};
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struct vega12_pcie_table {
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uint16_t count;
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uint8_t pcie_gen[MAX_PCIE_CONF];
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uint8_t pcie_lane[MAX_PCIE_CONF];
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uint32_t lclk[MAX_PCIE_CONF];
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};
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struct vega12_dpm_table {
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struct vega12_single_dpm_table soc_table;
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struct vega12_single_dpm_table gfx_table;
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struct vega12_single_dpm_table mem_table;
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struct vega12_single_dpm_table eclk_table;
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struct vega12_single_dpm_table vclk_table;
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struct vega12_single_dpm_table dclk_table;
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struct vega12_single_dpm_table dcef_table;
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struct vega12_single_dpm_table pixel_table;
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struct vega12_single_dpm_table display_table;
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struct vega12_single_dpm_table phy_table;
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struct vega12_pcie_table pcie_table;
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};
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#define VEGA12_MAX_LEAKAGE_COUNT 8
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struct vega12_leakage_voltage {
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uint16_t count;
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uint16_t leakage_id[VEGA12_MAX_LEAKAGE_COUNT];
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uint16_t actual_voltage[VEGA12_MAX_LEAKAGE_COUNT];
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};
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struct vega12_display_timing {
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uint32_t min_clock_in_sr;
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uint32_t num_existing_displays;
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};
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struct vega12_dpmlevel_enable_mask {
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uint32_t uvd_dpm_enable_mask;
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uint32_t vce_dpm_enable_mask;
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uint32_t samu_dpm_enable_mask;
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uint32_t sclk_dpm_enable_mask;
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uint32_t mclk_dpm_enable_mask;
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};
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struct vega12_vbios_boot_state {
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bool bsoc_vddc_lock;
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uint8_t uc_cooling_id;
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uint16_t vddc;
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uint16_t vddci;
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uint16_t mvddc;
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uint16_t vdd_gfx;
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uint32_t gfx_clock;
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uint32_t mem_clock;
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uint32_t soc_clock;
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uint32_t dcef_clock;
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};
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#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
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#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
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#define DPMTABLE_UPDATE_SCLK 0x00000004
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#define DPMTABLE_UPDATE_MCLK 0x00000008
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#define DPMTABLE_OD_UPDATE_VDDC 0x00000010
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struct vega12_smc_state_table {
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uint32_t soc_boot_level;
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uint32_t gfx_boot_level;
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uint32_t dcef_boot_level;
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uint32_t mem_boot_level;
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uint32_t uvd_boot_level;
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uint32_t vce_boot_level;
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uint32_t gfx_max_level;
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uint32_t mem_max_level;
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uint8_t vr_hot_gpio;
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uint8_t ac_dc_gpio;
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uint8_t therm_out_gpio;
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uint8_t therm_out_polarity;
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uint8_t therm_out_mode;
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PPTable_t pp_table;
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Watermarks_t water_marks_table;
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AvfsDebugTable_t avfs_debug_table;
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AvfsFuseOverride_t avfs_fuse_override_table;
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SmuMetrics_t smu_metrics;
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DriverSmuConfig_t driver_smu_config;
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DpmActivityMonitorCoeffInt_t dpm_activity_monitor_coeffint;
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OverDriveTable_t overdrive_table;
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};
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struct vega12_mclk_latency_entries {
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uint32_t frequency;
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uint32_t latency;
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};
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struct vega12_mclk_latency_table {
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uint32_t count;
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struct vega12_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER];
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};
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struct vega12_registry_data {
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uint64_t disallowed_features;
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uint8_t ac_dc_switch_gpio_support;
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uint8_t acg_loop_support;
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uint8_t clock_stretcher_support;
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uint8_t db_ramping_support;
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uint8_t didt_mode;
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uint8_t didt_support;
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uint8_t edc_didt_support;
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uint8_t force_dpm_high;
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uint8_t fuzzy_fan_control_support;
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uint8_t mclk_dpm_key_disabled;
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uint8_t od_state_in_dc_support;
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uint8_t pcie_lane_override;
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uint8_t pcie_speed_override;
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uint32_t pcie_clock_override;
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uint8_t pcie_dpm_key_disabled;
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uint8_t dcefclk_dpm_key_disabled;
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uint8_t prefetcher_dpm_key_disabled;
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uint8_t quick_transition_support;
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uint8_t regulator_hot_gpio_support;
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uint8_t master_deep_sleep_support;
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uint8_t gfx_clk_deep_sleep_support;
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uint8_t sclk_deep_sleep_support;
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uint8_t lclk_deep_sleep_support;
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uint8_t dce_fclk_deep_sleep_support;
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uint8_t sclk_dpm_key_disabled;
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uint8_t sclk_throttle_low_notification;
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uint8_t skip_baco_hardware;
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uint8_t socclk_dpm_key_disabled;
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uint8_t sq_ramping_support;
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uint8_t tcp_ramping_support;
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uint8_t td_ramping_support;
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uint8_t dbr_ramping_support;
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uint8_t gc_didt_support;
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uint8_t psm_didt_support;
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uint8_t thermal_support;
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uint8_t fw_ctf_enabled;
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uint8_t led_dpm_enabled;
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uint8_t fan_control_support;
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uint8_t ulv_support;
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uint8_t odn_feature_enable;
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uint8_t disable_water_mark;
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uint8_t disable_workload_policy;
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uint32_t force_workload_policy_mask;
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uint8_t disable_3d_fs_detection;
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uint8_t disable_pp_tuning;
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uint8_t disable_xlpp_tuning;
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uint32_t perf_ui_tuning_profile_turbo;
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uint32_t perf_ui_tuning_profile_powerSave;
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uint32_t perf_ui_tuning_profile_xl;
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uint16_t zrpm_stop_temp;
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uint16_t zrpm_start_temp;
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uint32_t stable_pstate_sclk_dpm_percentage;
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uint8_t fps_support;
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uint8_t vr0hot;
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uint8_t vr1hot;
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uint8_t disable_auto_wattman;
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uint32_t auto_wattman_debug;
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uint32_t auto_wattman_sample_period;
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uint8_t auto_wattman_threshold;
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uint8_t log_avfs_param;
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uint8_t enable_enginess;
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uint8_t custom_fan_support;
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uint8_t disable_pcc_limit_control;
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};
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struct vega12_odn_clock_voltage_dependency_table {
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uint32_t count;
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struct phm_ppt_v1_clock_voltage_dependency_record
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entries[MAX_REGULAR_DPM_NUMBER];
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};
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struct vega12_odn_dpm_table {
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struct vega12_odn_dpm_control control_gfxclk_state;
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struct vega12_odn_dpm_control control_memclk_state;
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struct phm_odn_clock_levels odn_core_clock_dpm_levels;
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struct phm_odn_clock_levels odn_memory_clock_dpm_levels;
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struct vega12_odn_clock_voltage_dependency_table vdd_dependency_on_sclk;
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struct vega12_odn_clock_voltage_dependency_table vdd_dependency_on_mclk;
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struct vega12_odn_clock_voltage_dependency_table vdd_dependency_on_socclk;
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uint32_t odn_mclk_min_limit;
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};
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struct vega12_odn_fan_table {
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uint32_t target_fan_speed;
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uint32_t target_temperature;
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uint32_t min_performance_clock;
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uint32_t min_fan_limit;
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bool force_fan_pwm;
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};
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struct vega12_hwmgr {
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struct vega12_dpm_table dpm_table;
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struct vega12_dpm_table golden_dpm_table;
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struct vega12_registry_data registry_data;
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struct vega12_vbios_boot_state vbios_boot_state;
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struct vega12_mclk_latency_table mclk_latency_table;
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struct vega12_leakage_voltage vddc_leakage;
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uint32_t vddc_control;
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struct pp_atomfwctrl_voltage_table vddc_voltage_table;
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uint32_t mvdd_control;
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struct pp_atomfwctrl_voltage_table mvdd_voltage_table;
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uint32_t vddci_control;
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struct pp_atomfwctrl_voltage_table vddci_voltage_table;
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uint32_t active_auto_throttle_sources;
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uint32_t water_marks_bitmap;
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struct vega12_bacos bacos;
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struct vega12_odn_dpm_table odn_dpm_table;
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struct vega12_odn_fan_table odn_fan_table;
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/* ---- General data ---- */
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uint8_t need_update_dpm_table;
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bool cac_enabled;
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bool battery_state;
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bool is_tlu_enabled;
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bool avfs_exist;
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uint32_t low_sclk_interrupt_threshold;
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||||
uint32_t total_active_cus;
|
||||
|
||||
struct vega12_display_timing display_timing;
|
||||
|
||||
/* ---- Vega12 Dyn Register Settings ---- */
|
||||
|
||||
uint32_t debug_settings;
|
||||
uint32_t lowest_uclk_reserved_for_ulv;
|
||||
uint32_t gfxclk_average_alpha;
|
||||
uint32_t socclk_average_alpha;
|
||||
uint32_t uclk_average_alpha;
|
||||
uint32_t gfx_activity_average_alpha;
|
||||
uint32_t display_voltage_mode;
|
||||
uint32_t dcef_clk_quad_eqn_a;
|
||||
uint32_t dcef_clk_quad_eqn_b;
|
||||
uint32_t dcef_clk_quad_eqn_c;
|
||||
uint32_t disp_clk_quad_eqn_a;
|
||||
uint32_t disp_clk_quad_eqn_b;
|
||||
uint32_t disp_clk_quad_eqn_c;
|
||||
uint32_t pixel_clk_quad_eqn_a;
|
||||
uint32_t pixel_clk_quad_eqn_b;
|
||||
uint32_t pixel_clk_quad_eqn_c;
|
||||
uint32_t phy_clk_quad_eqn_a;
|
||||
uint32_t phy_clk_quad_eqn_b;
|
||||
uint32_t phy_clk_quad_eqn_c;
|
||||
|
||||
/* ---- Thermal Temperature Setting ---- */
|
||||
struct vega12_dpmlevel_enable_mask dpm_level_enable_mask;
|
||||
|
||||
/* ---- Power Gating States ---- */
|
||||
bool uvd_power_gated;
|
||||
bool vce_power_gated;
|
||||
bool samu_power_gated;
|
||||
bool need_long_memory_training;
|
||||
|
||||
/* Internal settings to apply the application power optimization parameters */
|
||||
bool apply_optimized_settings;
|
||||
uint32_t disable_dpm_mask;
|
||||
|
||||
/* ---- Overdrive next setting ---- */
|
||||
uint32_t apply_overdrive_next_settings_mask;
|
||||
|
||||
/* ---- Workload Mask ---- */
|
||||
uint32_t workload_mask;
|
||||
|
||||
/* ---- SMU9 ---- */
|
||||
uint32_t smu_version;
|
||||
struct smu_features smu_features[GNLD_FEATURES_MAX];
|
||||
struct vega12_smc_state_table smc_state_table;
|
||||
};
|
||||
|
||||
#define VEGA12_DPM2_NEAR_TDP_DEC 10
|
||||
#define VEGA12_DPM2_ABOVE_SAFE_INC 5
|
||||
#define VEGA12_DPM2_BELOW_SAFE_INC 20
|
||||
|
||||
#define VEGA12_DPM2_LTA_WINDOW_SIZE 7
|
||||
|
||||
#define VEGA12_DPM2_LTS_TRUNCATE 0
|
||||
|
||||
#define VEGA12_DPM2_TDP_SAFE_LIMIT_PERCENT 80
|
||||
|
||||
#define VEGA12_DPM2_MAXPS_PERCENT_M 90
|
||||
#define VEGA12_DPM2_MAXPS_PERCENT_H 90
|
||||
|
||||
#define VEGA12_DPM2_PWREFFICIENCYRATIO_MARGIN 50
|
||||
|
||||
#define VEGA12_DPM2_SQ_RAMP_MAX_POWER 0x3FFF
|
||||
#define VEGA12_DPM2_SQ_RAMP_MIN_POWER 0x12
|
||||
#define VEGA12_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15
|
||||
#define VEGA12_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE 0x1E
|
||||
#define VEGA12_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO 0xF
|
||||
|
||||
#define VEGA12_VOLTAGE_CONTROL_NONE 0x0
|
||||
#define VEGA12_VOLTAGE_CONTROL_BY_GPIO 0x1
|
||||
#define VEGA12_VOLTAGE_CONTROL_BY_SVID2 0x2
|
||||
#define VEGA12_VOLTAGE_CONTROL_MERGED 0x3
|
||||
/* To convert to Q8.8 format for firmware */
|
||||
#define VEGA12_Q88_FORMAT_CONVERSION_UNIT 256
|
||||
|
||||
#define VEGA12_UNUSED_GPIO_PIN 0x7F
|
||||
|
||||
#define VEGA12_THERM_OUT_MODE_DISABLE 0x0
|
||||
#define VEGA12_THERM_OUT_MODE_THERM_ONLY 0x1
|
||||
#define VEGA12_THERM_OUT_MODE_THERM_VRHOT 0x2
|
||||
|
||||
#define PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT 0xffffffff
|
||||
#define PPREGKEY_VEGA12QUADRATICEQUATION_DFLT 0xffffffff
|
||||
|
||||
#define PPVEGA12_VEGA12GFXCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */
|
||||
#define PPVEGA12_VEGA12SOCCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */
|
||||
#define PPVEGA12_VEGA12UCLKCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */
|
||||
#define PPVEGA12_VEGA12GFXACTIVITYAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */
|
||||
#define PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT 0xffffffff
|
||||
#define PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT 0xffffffff
|
||||
#define PPREGKEY_VEGA12QUADRATICEQUATION_DFLT 0xffffffff
|
||||
|
||||
#define VEGA12_UMD_PSTATE_GFXCLK_LEVEL 0x3
|
||||
#define VEGA12_UMD_PSTATE_SOCCLK_LEVEL 0x3
|
||||
#define VEGA12_UMD_PSTATE_MCLK_LEVEL 0x2
|
||||
|
||||
int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
|
||||
|
||||
#endif /* _VEGA12_HWMGR_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* Copyright 2017 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#ifndef _VEGA12_POWERTUNE_H_
|
||||
#define _VEGA12_POWERTUNE_H_
|
||||
|
||||
enum vega12_didt_config_reg_type {
|
||||
VEGA12_CONFIGREG_DIDT = 0,
|
||||
VEGA12_CONFIGREG_GCCAC,
|
||||
VEGA12_CONFIGREG_SECAC
|
||||
};
|
||||
|
||||
/* PowerContainment Features */
|
||||
#define POWERCONTAINMENT_FEATURE_DTE 0x00000001
|
||||
#define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002
|
||||
#define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004
|
||||
|
||||
struct vega12_didt_config_reg {
|
||||
uint32_t offset;
|
||||
uint32_t mask;
|
||||
uint32_t shift;
|
||||
uint32_t value;
|
||||
};
|
||||
|
||||
int vega12_enable_power_containment(struct pp_hwmgr *hwmgr);
|
||||
int vega12_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
|
||||
int vega12_power_control_set_level(struct pp_hwmgr *hwmgr);
|
||||
int vega12_disable_power_containment(struct pp_hwmgr *hwmgr);
|
||||
|
||||
int vega12_enable_didt_config(struct pp_hwmgr *hwmgr);
|
||||
int vega12_disable_didt_config(struct pp_hwmgr *hwmgr);
|
||||
|
||||
#endif /* _VEGA12_POWERTUNE_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,430 @@
|
|||
/*
|
||||
* Copyright 2017 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/fb.h>
|
||||
|
||||
#include "vega12/smu9_driver_if.h"
|
||||
#include "vega12_processpptables.h"
|
||||
#include "ppatomfwctrl.h"
|
||||
#include "atomfirmware.h"
|
||||
#include "pp_debug.h"
|
||||
#include "cgs_common.h"
|
||||
#include "vega12_pptable.h"
|
||||
|
||||
static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
|
||||
enum phm_platform_caps cap)
|
||||
{
|
||||
if (enable)
|
||||
phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap);
|
||||
else
|
||||
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap);
|
||||
}
|
||||
|
||||
static const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
int index = GetIndexIntoMasterDataTable(powerplayinfo);
|
||||
|
||||
u16 size;
|
||||
u8 frev, crev;
|
||||
const void *table_address = hwmgr->soft_pp_table;
|
||||
|
||||
if (!table_address) {
|
||||
table_address = (ATOM_Vega12_POWERPLAYTABLE *)
|
||||
cgs_atom_get_data_table(hwmgr->device, index,
|
||||
&size, &frev, &crev);
|
||||
|
||||
hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/
|
||||
hwmgr->soft_pp_table_size = size;
|
||||
}
|
||||
|
||||
return table_address;
|
||||
}
|
||||
|
||||
static int check_powerplay_tables(
|
||||
struct pp_hwmgr *hwmgr,
|
||||
const ATOM_Vega12_POWERPLAYTABLE *powerplay_table)
|
||||
{
|
||||
PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >=
|
||||
ATOM_VEGA12_TABLE_REVISION_VEGA12),
|
||||
"Unsupported PPTable format!", return -1);
|
||||
PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0,
|
||||
"Invalid PowerPlay Table!", return -1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps)
|
||||
{
|
||||
set_hw_cap(
|
||||
hwmgr,
|
||||
0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_POWERPLAY),
|
||||
PHM_PlatformCaps_PowerPlaySupport);
|
||||
|
||||
set_hw_cap(
|
||||
hwmgr,
|
||||
0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_SBIOSPOWERSOURCE),
|
||||
PHM_PlatformCaps_BiosPowerSourceControl);
|
||||
|
||||
set_hw_cap(
|
||||
hwmgr,
|
||||
0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_BACO),
|
||||
PHM_PlatformCaps_BACO);
|
||||
|
||||
set_hw_cap(
|
||||
hwmgr,
|
||||
0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_BAMACO),
|
||||
PHM_PlatformCaps_BAMACO);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int copy_clock_limits_array(
|
||||
struct pp_hwmgr *hwmgr,
|
||||
uint32_t **pptable_info_array,
|
||||
const uint32_t *pptable_array)
|
||||
{
|
||||
uint32_t array_size, i;
|
||||
uint32_t *table;
|
||||
|
||||
array_size = sizeof(uint32_t) * ATOM_VEGA12_PPCLOCK_COUNT;
|
||||
|
||||
table = kzalloc(array_size, GFP_KERNEL);
|
||||
if (NULL == table)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < ATOM_VEGA12_PPCLOCK_COUNT; i++)
|
||||
table[i] = pptable_array[i];
|
||||
|
||||
*pptable_info_array = table;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int copy_overdrive_settings_limits_array(
|
||||
struct pp_hwmgr *hwmgr,
|
||||
uint32_t **pptable_info_array,
|
||||
const uint32_t *pptable_array)
|
||||
{
|
||||
uint32_t array_size, i;
|
||||
uint32_t *table;
|
||||
|
||||
array_size = sizeof(uint32_t) * ATOM_VEGA12_ODSETTING_COUNT;
|
||||
|
||||
table = kzalloc(array_size, GFP_KERNEL);
|
||||
if (NULL == table)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < ATOM_VEGA12_ODSETTING_COUNT; i++)
|
||||
table[i] = pptable_array[i];
|
||||
|
||||
*pptable_info_array = table;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int append_vbios_pptable(struct pp_hwmgr *hwmgr, PPTable_t *ppsmc_pptable)
|
||||
{
|
||||
struct pp_atomfwctrl_smc_dpm_parameters smc_dpm_table;
|
||||
|
||||
PP_ASSERT_WITH_CODE(
|
||||
pp_atomfwctrl_get_smc_dpm_information(hwmgr, &smc_dpm_table) == 0,
|
||||
"[appendVbiosPPTable] Failed to retrieve Smc Dpm Table from VBIOS!",
|
||||
return -1);
|
||||
|
||||
ppsmc_pptable->Liquid1_I2C_address = smc_dpm_table.liquid1_i2c_address;
|
||||
ppsmc_pptable->Liquid2_I2C_address = smc_dpm_table.liquid2_i2c_address;
|
||||
ppsmc_pptable->Vr_I2C_address = smc_dpm_table.vr_i2c_address;
|
||||
ppsmc_pptable->Plx_I2C_address = smc_dpm_table.plx_i2c_address;
|
||||
|
||||
ppsmc_pptable->Liquid_I2C_LineSCL = smc_dpm_table.liquid_i2c_linescl;
|
||||
ppsmc_pptable->Liquid_I2C_LineSDA = smc_dpm_table.liquid_i2c_linesda;
|
||||
ppsmc_pptable->Vr_I2C_LineSCL = smc_dpm_table.vr_i2c_linescl;
|
||||
ppsmc_pptable->Vr_I2C_LineSDA = smc_dpm_table.vr_i2c_linesda;
|
||||
|
||||
ppsmc_pptable->Plx_I2C_LineSCL = smc_dpm_table.plx_i2c_linescl;
|
||||
ppsmc_pptable->Plx_I2C_LineSDA = smc_dpm_table.plx_i2c_linesda;
|
||||
ppsmc_pptable->VrSensorPresent = smc_dpm_table.vrsensorpresent;
|
||||
ppsmc_pptable->LiquidSensorPresent = smc_dpm_table.liquidsensorpresent;
|
||||
|
||||
ppsmc_pptable->MaxVoltageStepGfx = smc_dpm_table.maxvoltagestepgfx;
|
||||
ppsmc_pptable->MaxVoltageStepSoc = smc_dpm_table.maxvoltagestepsoc;
|
||||
|
||||
ppsmc_pptable->VddGfxVrMapping = smc_dpm_table.vddgfxvrmapping;
|
||||
ppsmc_pptable->VddSocVrMapping = smc_dpm_table.vddsocvrmapping;
|
||||
ppsmc_pptable->VddMem0VrMapping = smc_dpm_table.vddmem0vrmapping;
|
||||
ppsmc_pptable->VddMem1VrMapping = smc_dpm_table.vddmem1vrmapping;
|
||||
|
||||
ppsmc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table.gfxulvphasesheddingmask;
|
||||
ppsmc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table.soculvphasesheddingmask;
|
||||
|
||||
ppsmc_pptable->GfxMaxCurrent = smc_dpm_table.gfxmaxcurrent;
|
||||
ppsmc_pptable->GfxOffset = smc_dpm_table.gfxoffset;
|
||||
ppsmc_pptable->Padding_TelemetryGfx = smc_dpm_table.padding_telemetrygfx;
|
||||
|
||||
ppsmc_pptable->SocMaxCurrent = smc_dpm_table.socmaxcurrent;
|
||||
ppsmc_pptable->SocOffset = smc_dpm_table.socoffset;
|
||||
ppsmc_pptable->Padding_TelemetrySoc = smc_dpm_table.padding_telemetrysoc;
|
||||
|
||||
ppsmc_pptable->Mem0MaxCurrent = smc_dpm_table.mem0maxcurrent;
|
||||
ppsmc_pptable->Mem0Offset = smc_dpm_table.mem0offset;
|
||||
ppsmc_pptable->Padding_TelemetryMem0 = smc_dpm_table.padding_telemetrymem0;
|
||||
|
||||
ppsmc_pptable->Mem1MaxCurrent = smc_dpm_table.mem1maxcurrent;
|
||||
ppsmc_pptable->Mem1Offset = smc_dpm_table.mem1offset;
|
||||
ppsmc_pptable->Padding_TelemetryMem1 = smc_dpm_table.padding_telemetrymem1;
|
||||
|
||||
ppsmc_pptable->AcDcGpio = smc_dpm_table.acdcgpio;
|
||||
ppsmc_pptable->AcDcPolarity = smc_dpm_table.acdcpolarity;
|
||||
ppsmc_pptable->VR0HotGpio = smc_dpm_table.vr0hotgpio;
|
||||
ppsmc_pptable->VR0HotPolarity = smc_dpm_table.vr0hotpolarity;
|
||||
|
||||
ppsmc_pptable->VR1HotGpio = smc_dpm_table.vr1hotgpio;
|
||||
ppsmc_pptable->VR1HotPolarity = smc_dpm_table.vr1hotpolarity;
|
||||
ppsmc_pptable->Padding1 = smc_dpm_table.padding1;
|
||||
ppsmc_pptable->Padding2 = smc_dpm_table.padding2;
|
||||
|
||||
ppsmc_pptable->LedPin0 = smc_dpm_table.ledpin0;
|
||||
ppsmc_pptable->LedPin1 = smc_dpm_table.ledpin1;
|
||||
ppsmc_pptable->LedPin2 = smc_dpm_table.ledpin2;
|
||||
|
||||
ppsmc_pptable->GfxclkSpreadEnabled = smc_dpm_table.gfxclkspreadenabled;
|
||||
ppsmc_pptable->GfxclkSpreadPercent = smc_dpm_table.gfxclkspreadpercent;
|
||||
ppsmc_pptable->GfxclkSpreadFreq = smc_dpm_table.gfxclkspreadfreq;
|
||||
|
||||
ppsmc_pptable->UclkSpreadEnabled = 0;
|
||||
ppsmc_pptable->UclkSpreadPercent = smc_dpm_table.uclkspreadpercent;
|
||||
ppsmc_pptable->UclkSpreadFreq = smc_dpm_table.uclkspreadfreq;
|
||||
|
||||
ppsmc_pptable->SocclkSpreadEnabled = 0;
|
||||
ppsmc_pptable->SocclkSpreadPercent = smc_dpm_table.socclkspreadpercent;
|
||||
ppsmc_pptable->SocclkSpreadFreq = smc_dpm_table.socclkspreadfreq;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define VEGA12_ENGINECLOCK_HARDMAX 198000
|
||||
static int init_powerplay_table_information(
|
||||
struct pp_hwmgr *hwmgr,
|
||||
const ATOM_Vega12_POWERPLAYTABLE *powerplay_table)
|
||||
{
|
||||
struct phm_ppt_v3_information *pptable_information =
|
||||
(struct phm_ppt_v3_information *)hwmgr->pptable;
|
||||
uint32_t disable_power_control = 0;
|
||||
int result;
|
||||
|
||||
hwmgr->thermal_controller.ucType = powerplay_table->ucThermalControllerType;
|
||||
pptable_information->uc_thermal_controller_type = powerplay_table->ucThermalControllerType;
|
||||
|
||||
set_hw_cap(hwmgr,
|
||||
ATOM_VEGA12_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType,
|
||||
PHM_PlatformCaps_ThermalController);
|
||||
|
||||
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
|
||||
|
||||
if (powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_GFXCLKFMAX] > VEGA12_ENGINECLOCK_HARDMAX)
|
||||
hwmgr->platform_descriptor.overdriveLimit.engineClock = VEGA12_ENGINECLOCK_HARDMAX;
|
||||
else
|
||||
hwmgr->platform_descriptor.overdriveLimit.engineClock = powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_GFXCLKFMAX];
|
||||
hwmgr->platform_descriptor.overdriveLimit.memoryClock = powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_UCLKFMAX];
|
||||
|
||||
copy_overdrive_settings_limits_array(hwmgr, &pptable_information->od_settings_max, powerplay_table->ODSettingsMax);
|
||||
copy_overdrive_settings_limits_array(hwmgr, &pptable_information->od_settings_min, powerplay_table->ODSettingsMin);
|
||||
|
||||
/* hwmgr->platformDescriptor.minOverdriveVDDC = 0;
|
||||
hwmgr->platformDescriptor.maxOverdriveVDDC = 0;
|
||||
hwmgr->platformDescriptor.overdriveVDDCStep = 0; */
|
||||
|
||||
if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0
|
||||
&& hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0)
|
||||
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ACOverdriveSupport);
|
||||
|
||||
pptable_information->us_small_power_limit1 = powerplay_table->usSmallPowerLimit1;
|
||||
pptable_information->us_small_power_limit2 = powerplay_table->usSmallPowerLimit2;
|
||||
pptable_information->us_boost_power_limit = powerplay_table->usBoostPowerLimit;
|
||||
pptable_information->us_od_turbo_power_limit = powerplay_table->usODTurboPowerLimit;
|
||||
pptable_information->us_od_powersave_power_limit = powerplay_table->usODPowerSavePowerLimit;
|
||||
|
||||
pptable_information->us_software_shutdown_temp = powerplay_table->usSoftwareShutdownTemp;
|
||||
|
||||
hwmgr->platform_descriptor.TDPODLimit = (uint16_t)powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_POWERPERCENTAGE];
|
||||
|
||||
disable_power_control = 0;
|
||||
if (!disable_power_control) {
|
||||
/* enable TDP overdrive (PowerControl) feature as well if supported */
|
||||
if (hwmgr->platform_descriptor.TDPODLimit)
|
||||
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
|
||||
PHM_PlatformCaps_PowerControl);
|
||||
}
|
||||
|
||||
copy_clock_limits_array(hwmgr, &pptable_information->power_saving_clock_max, powerplay_table->PowerSavingClockMax);
|
||||
copy_clock_limits_array(hwmgr, &pptable_information->power_saving_clock_min, powerplay_table->PowerSavingClockMin);
|
||||
|
||||
pptable_information->smc_pptable = (PPTable_t *)kmalloc(sizeof(PPTable_t), GFP_KERNEL);
|
||||
if (pptable_information->smc_pptable == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
memcpy(pptable_information->smc_pptable, &(powerplay_table->smcPPTable), sizeof(PPTable_t));
|
||||
|
||||
result = append_vbios_pptable(hwmgr, (pptable_information->smc_pptable));
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
int vega12_pp_tables_initialize(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
int result = 0;
|
||||
const ATOM_Vega12_POWERPLAYTABLE *powerplay_table;
|
||||
|
||||
hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v3_information), GFP_KERNEL);
|
||||
PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL),
|
||||
"Failed to allocate hwmgr->pptable!", return -ENOMEM);
|
||||
|
||||
powerplay_table = get_powerplay_table(hwmgr);
|
||||
PP_ASSERT_WITH_CODE((powerplay_table != NULL),
|
||||
"Missing PowerPlay Table!", return -1);
|
||||
|
||||
result = check_powerplay_tables(hwmgr, powerplay_table);
|
||||
PP_ASSERT_WITH_CODE((result == 0),
|
||||
"check_powerplay_tables failed", return result);
|
||||
|
||||
result = set_platform_caps(hwmgr,
|
||||
le32_to_cpu(powerplay_table->ulPlatformCaps));
|
||||
PP_ASSERT_WITH_CODE((result == 0),
|
||||
"set_platform_caps failed", return result);
|
||||
|
||||
result = init_powerplay_table_information(hwmgr, powerplay_table);
|
||||
PP_ASSERT_WITH_CODE((result == 0),
|
||||
"init_powerplay_table_information failed", return result);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static int vega12_pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
struct phm_ppt_v3_information *pp_table_info =
|
||||
(struct phm_ppt_v3_information *)(hwmgr->pptable);
|
||||
|
||||
kfree(pp_table_info->power_saving_clock_max);
|
||||
pp_table_info->power_saving_clock_max = NULL;
|
||||
|
||||
kfree(pp_table_info->power_saving_clock_min);
|
||||
pp_table_info->power_saving_clock_min = NULL;
|
||||
|
||||
kfree(pp_table_info->od_settings_max);
|
||||
pp_table_info->od_settings_max = NULL;
|
||||
|
||||
kfree(pp_table_info->od_settings_min);
|
||||
pp_table_info->od_settings_min = NULL;
|
||||
|
||||
kfree(pp_table_info->smc_pptable);
|
||||
pp_table_info->smc_pptable = NULL;
|
||||
|
||||
kfree(hwmgr->pptable);
|
||||
hwmgr->pptable = NULL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct pp_table_func vega12_pptable_funcs = {
|
||||
.pptable_init = vega12_pp_tables_initialize,
|
||||
.pptable_fini = vega12_pp_tables_uninitialize,
|
||||
};
|
||||
|
||||
#if 0
|
||||
static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr,
|
||||
uint16_t classification, uint16_t classification2)
|
||||
{
|
||||
uint32_t result = 0;
|
||||
|
||||
if (classification & ATOM_PPLIB_CLASSIFICATION_BOOT)
|
||||
result |= PP_StateClassificationFlag_Boot;
|
||||
|
||||
if (classification & ATOM_PPLIB_CLASSIFICATION_THERMAL)
|
||||
result |= PP_StateClassificationFlag_Thermal;
|
||||
|
||||
if (classification & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE)
|
||||
result |= PP_StateClassificationFlag_LimitedPowerSource;
|
||||
|
||||
if (classification & ATOM_PPLIB_CLASSIFICATION_REST)
|
||||
result |= PP_StateClassificationFlag_Rest;
|
||||
|
||||
if (classification & ATOM_PPLIB_CLASSIFICATION_FORCED)
|
||||
result |= PP_StateClassificationFlag_Forced;
|
||||
|
||||
if (classification & ATOM_PPLIB_CLASSIFICATION_ACPI)
|
||||
result |= PP_StateClassificationFlag_ACPI;
|
||||
|
||||
if (classification2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2)
|
||||
result |= PP_StateClassificationFlag_LimitedPowerSource_2;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
int vega12_get_powerplay_table_entry(struct pp_hwmgr *hwmgr,
|
||||
uint32_t entry_index, struct pp_power_state *power_state,
|
||||
int (*call_back_func)(struct pp_hwmgr *, void *,
|
||||
struct pp_power_state *, void *, uint32_t))
|
||||
{
|
||||
int result = 0;
|
||||
const ATOM_Vega12_State_Array *state_arrays;
|
||||
const ATOM_Vega12_State *state_entry;
|
||||
const ATOM_Vega12_POWERPLAYTABLE *pp_table =
|
||||
get_powerplay_table(hwmgr);
|
||||
|
||||
PP_ASSERT_WITH_CODE(pp_table, "Missing PowerPlay Table!",
|
||||
return -1;);
|
||||
power_state->classification.bios_index = entry_index;
|
||||
|
||||
if (pp_table->sHeader.format_revision >=
|
||||
ATOM_Vega12_TABLE_REVISION_VEGA12) {
|
||||
state_arrays = (ATOM_Vega12_State_Array *)
|
||||
(((unsigned long)pp_table) +
|
||||
le16_to_cpu(pp_table->usStateArrayOffset));
|
||||
|
||||
PP_ASSERT_WITH_CODE(pp_table->usStateArrayOffset > 0,
|
||||
"Invalid PowerPlay Table State Array Offset.",
|
||||
return -1);
|
||||
PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0,
|
||||
"Invalid PowerPlay Table State Array.",
|
||||
return -1);
|
||||
PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries),
|
||||
"Invalid PowerPlay Table State Array Entry.",
|
||||
return -1);
|
||||
|
||||
state_entry = &(state_arrays->states[entry_index]);
|
||||
|
||||
result = call_back_func(hwmgr, (void *)state_entry, power_state,
|
||||
(void *)pp_table,
|
||||
make_classification_flags(hwmgr,
|
||||
le16_to_cpu(state_entry->usClassification),
|
||||
le16_to_cpu(state_entry->usClassification2)));
|
||||
}
|
||||
|
||||
if (!result && (power_state->classification.flags &
|
||||
PP_StateClassificationFlag_Boot))
|
||||
result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware));
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* Copyright 2017 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef VEGA12_PROCESSPPTABLES_H
|
||||
#define VEGA12_PROCESSPPTABLES_H
|
||||
|
||||
#include "hwmgr.h"
|
||||
|
||||
enum Vega12_I2CLineID {
|
||||
Vega12_I2CLineID_DDC1 = 0x90,
|
||||
Vega12_I2CLineID_DDC2 = 0x91,
|
||||
Vega12_I2CLineID_DDC3 = 0x92,
|
||||
Vega12_I2CLineID_DDC4 = 0x93,
|
||||
Vega12_I2CLineID_DDC5 = 0x94,
|
||||
Vega12_I2CLineID_DDC6 = 0x95,
|
||||
Vega12_I2CLineID_SCLSDA = 0x96,
|
||||
Vega12_I2CLineID_DDCVGA = 0x97
|
||||
};
|
||||
|
||||
#define Vega12_I2C_DDC1DATA 0
|
||||
#define Vega12_I2C_DDC1CLK 1
|
||||
#define Vega12_I2C_DDC2DATA 2
|
||||
#define Vega12_I2C_DDC2CLK 3
|
||||
#define Vega12_I2C_DDC3DATA 4
|
||||
#define Vega12_I2C_DDC3CLK 5
|
||||
#define Vega12_I2C_SDA 40
|
||||
#define Vega12_I2C_SCL 41
|
||||
#define Vega12_I2C_DDC4DATA 65
|
||||
#define Vega12_I2C_DDC4CLK 66
|
||||
#define Vega12_I2C_DDC5DATA 0x48
|
||||
#define Vega12_I2C_DDC5CLK 0x49
|
||||
#define Vega12_I2C_DDC6DATA 0x4a
|
||||
#define Vega12_I2C_DDC6CLK 0x4b
|
||||
#define Vega12_I2C_DDCVGADATA 0x4c
|
||||
#define Vega12_I2C_DDCVGACLK 0x4d
|
||||
|
||||
extern const struct pp_table_func vega12_pptable_funcs;
|
||||
#endif
|
||||
|
|
@ -0,0 +1,324 @@
|
|||
/*
|
||||
* Copyright 2017 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "vega12_thermal.h"
|
||||
#include "vega12_hwmgr.h"
|
||||
#include "vega12_smumgr.h"
|
||||
#include "vega12_ppsmc.h"
|
||||
#include "vega12_inc.h"
|
||||
#include "pp_soc15.h"
|
||||
#include "pp_debug.h"
|
||||
|
||||
static int vega12_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
|
||||
{
|
||||
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
|
||||
PPSMC_MSG_GetCurrentRpm),
|
||||
"Attempt to get current RPM from SMC Failed!",
|
||||
return -1);
|
||||
PP_ASSERT_WITH_CODE(!vega12_read_arg_from_smc(hwmgr,
|
||||
current_rpm),
|
||||
"Attempt to read current RPM from SMC Failed!",
|
||||
return -1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int vega12_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
|
||||
struct phm_fan_speed_info *fan_speed_info)
|
||||
{
|
||||
memset(fan_speed_info, 0, sizeof(*fan_speed_info));
|
||||
fan_speed_info->supports_percent_read = false;
|
||||
fan_speed_info->supports_percent_write = false;
|
||||
fan_speed_info->supports_rpm_read = true;
|
||||
fan_speed_info->supports_rpm_write = true;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int vega12_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
|
||||
{
|
||||
*speed = 0;
|
||||
|
||||
return vega12_get_current_rpm(hwmgr, speed);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn vega12_enable_fan_control_feature
|
||||
* @brief Enables the SMC Fan Control Feature.
|
||||
*
|
||||
* @param hwmgr - the address of the powerplay hardware manager.
|
||||
* @return 0 on success. -1 otherwise.
|
||||
*/
|
||||
static int vega12_enable_fan_control_feature(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
#if 0
|
||||
struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
|
||||
|
||||
if (data->smu_features[GNLD_FAN_CONTROL].supported) {
|
||||
PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(
|
||||
hwmgr, true,
|
||||
data->smu_features[GNLD_FAN_CONTROL].
|
||||
smu_feature_bitmap),
|
||||
"Attempt to Enable FAN CONTROL feature Failed!",
|
||||
return -1);
|
||||
data->smu_features[GNLD_FAN_CONTROL].enabled = true;
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int vega12_disable_fan_control_feature(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
#if 0
|
||||
struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
|
||||
|
||||
if (data->smu_features[GNLD_FAN_CONTROL].supported) {
|
||||
PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(
|
||||
hwmgr, false,
|
||||
data->smu_features[GNLD_FAN_CONTROL].
|
||||
smu_feature_bitmap),
|
||||
"Attempt to Enable FAN CONTROL feature Failed!",
|
||||
return -1);
|
||||
data->smu_features[GNLD_FAN_CONTROL].enabled = false;
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int vega12_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
|
||||
|
||||
if (data->smu_features[GNLD_FAN_CONTROL].supported)
|
||||
PP_ASSERT_WITH_CODE(
|
||||
!vega12_enable_fan_control_feature(hwmgr),
|
||||
"Attempt to Enable SMC FAN CONTROL Feature Failed!",
|
||||
return -1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int vega12_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
|
||||
|
||||
if (data->smu_features[GNLD_FAN_CONTROL].supported)
|
||||
PP_ASSERT_WITH_CODE(!vega12_disable_fan_control_feature(hwmgr),
|
||||
"Attempt to Disable SMC FAN CONTROL Feature Failed!",
|
||||
return -1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Reset Fan Speed to default.
|
||||
* @param hwmgr the address of the powerplay hardware manager.
|
||||
* @exception Always succeeds.
|
||||
*/
|
||||
int vega12_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
return vega12_fan_ctrl_start_smc_fan_control(hwmgr);
|
||||
}
|
||||
|
||||
/**
|
||||
* Reads the remote temperature from the SIslands thermal controller.
|
||||
*
|
||||
* @param hwmgr The address of the hardware manager.
|
||||
*/
|
||||
int vega12_thermal_get_temperature(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
int temp = 0;
|
||||
uint32_t reg;
|
||||
|
||||
reg = soc15_get_register_offset(THM_HWID, 0,
|
||||
mmCG_MULT_THERMAL_STATUS_BASE_IDX, mmCG_MULT_THERMAL_STATUS);
|
||||
|
||||
temp = cgs_read_register(hwmgr->device, reg);
|
||||
|
||||
temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
|
||||
CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
|
||||
|
||||
temp = temp & 0x1ff;
|
||||
|
||||
temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
|
||||
return temp;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the requested temperature range for high and low alert signals
|
||||
*
|
||||
* @param hwmgr The address of the hardware manager.
|
||||
* @param range Temperature range to be programmed for
|
||||
* high and low alert signals
|
||||
* @exception PP_Result_BadInput if the input data is not valid.
|
||||
*/
|
||||
static int vega12_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
|
||||
struct PP_TemperatureRange *range)
|
||||
{
|
||||
int low = VEGA12_THERMAL_MINIMUM_ALERT_TEMP *
|
||||
PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
|
||||
int high = VEGA12_THERMAL_MAXIMUM_ALERT_TEMP *
|
||||
PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
|
||||
uint32_t val, reg;
|
||||
|
||||
if (low < range->min)
|
||||
low = range->min;
|
||||
if (high > range->max)
|
||||
high = range->max;
|
||||
|
||||
if (low > high)
|
||||
return -EINVAL;
|
||||
|
||||
reg = soc15_get_register_offset(THM_HWID, 0,
|
||||
mmTHM_THERMAL_INT_CTRL_BASE_IDX, mmTHM_THERMAL_INT_CTRL);
|
||||
|
||||
val = cgs_read_register(hwmgr->device, reg);
|
||||
|
||||
val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
|
||||
val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
|
||||
val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
|
||||
val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
|
||||
val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
|
||||
|
||||
cgs_write_register(hwmgr->device, reg, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable thermal alerts on the RV770 thermal controller.
|
||||
*
|
||||
* @param hwmgr The address of the hardware manager.
|
||||
*/
|
||||
static int vega12_thermal_enable_alert(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
uint32_t val = 0;
|
||||
uint32_t reg;
|
||||
|
||||
val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
|
||||
val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
|
||||
val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
|
||||
|
||||
reg = soc15_get_register_offset(THM_HWID, 0, mmTHM_THERMAL_INT_ENA_BASE_IDX, mmTHM_THERMAL_INT_ENA);
|
||||
cgs_write_register(hwmgr->device, reg, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Disable thermal alerts on the RV770 thermal controller.
|
||||
* @param hwmgr The address of the hardware manager.
|
||||
*/
|
||||
int vega12_thermal_disable_alert(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
reg = soc15_get_register_offset(THM_HWID, 0, mmTHM_THERMAL_INT_ENA_BASE_IDX, mmTHM_THERMAL_INT_ENA);
|
||||
cgs_write_register(hwmgr->device, reg, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Uninitialize the thermal controller.
|
||||
* Currently just disables alerts.
|
||||
* @param hwmgr The address of the hardware manager.
|
||||
*/
|
||||
int vega12_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
int result = vega12_thermal_disable_alert(hwmgr);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set up the fan table to control the fan using the SMC.
|
||||
* @param hwmgr the address of the powerplay hardware manager.
|
||||
* @param pInput the pointer to input data
|
||||
* @param pOutput the pointer to output data
|
||||
* @param pStorage the pointer to temporary storage
|
||||
* @param Result the last failure code
|
||||
* @return result from set temperature range routine
|
||||
*/
|
||||
int vega12_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
int ret;
|
||||
struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
|
||||
PPTable_t *table = &(data->smc_state_table.pp_table);
|
||||
|
||||
ret = smum_send_msg_to_smc_with_parameter(hwmgr,
|
||||
PPSMC_MSG_SetFanTemperatureTarget,
|
||||
(uint32_t)table->FanTargetTemperature);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* Start the fan control on the SMC.
|
||||
* @param hwmgr the address of the powerplay hardware manager.
|
||||
* @param pInput the pointer to input data
|
||||
* @param pOutput the pointer to output data
|
||||
* @param pStorage the pointer to temporary storage
|
||||
* @param Result the last failure code
|
||||
* @return result from set temperature range routine
|
||||
*/
|
||||
int vega12_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
/* If the fantable setup has failed we could have disabled
|
||||
* PHM_PlatformCaps_MicrocodeFanControl even after
|
||||
* this function was included in the table.
|
||||
* Make sure that we still think controlling the fan is OK.
|
||||
*/
|
||||
if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
|
||||
vega12_fan_ctrl_start_smc_fan_control(hwmgr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int vega12_start_thermal_controller(struct pp_hwmgr *hwmgr,
|
||||
struct PP_TemperatureRange *range)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (range == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
ret = vega12_thermal_set_temperature_range(hwmgr, range);
|
||||
if (ret)
|
||||
return -EINVAL;
|
||||
|
||||
vega12_thermal_enable_alert(hwmgr);
|
||||
/* We should restrict performance levels to low before we halt the SMC.
|
||||
* On the other hand we are still in boot state when we do this
|
||||
* so it would be pointless.
|
||||
* If this assumption changes we have to revisit this table.
|
||||
*/
|
||||
ret = vega12_thermal_setup_fan_table(hwmgr);
|
||||
if (ret)
|
||||
return -EINVAL;
|
||||
|
||||
vega12_thermal_start_smc_fan_control(hwmgr);
|
||||
|
||||
return 0;
|
||||
};
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* Copyright 2017 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef VEGA12_THERMAL_H
|
||||
#define VEGA12_THERMAL_H
|
||||
|
||||
#include "hwmgr.h"
|
||||
|
||||
struct vega12_temperature {
|
||||
uint16_t edge_temp;
|
||||
uint16_t hot_spot_temp;
|
||||
uint16_t hbm_temp;
|
||||
uint16_t vr_soc_temp;
|
||||
uint16_t vr_mem_temp;
|
||||
uint16_t liquid1_temp;
|
||||
uint16_t liquid2_temp;
|
||||
uint16_t plx_temp;
|
||||
};
|
||||
|
||||
#define VEGA12_THERMAL_HIGH_ALERT_MASK 0x1
|
||||
#define VEGA12_THERMAL_LOW_ALERT_MASK 0x2
|
||||
|
||||
#define VEGA12_THERMAL_MINIMUM_TEMP_READING -256
|
||||
#define VEGA12_THERMAL_MAXIMUM_TEMP_READING 255
|
||||
|
||||
#define VEGA12_THERMAL_MINIMUM_ALERT_TEMP 0
|
||||
#define VEGA12_THERMAL_MAXIMUM_ALERT_TEMP 255
|
||||
|
||||
#define FDO_PWM_MODE_STATIC 1
|
||||
#define FDO_PWM_MODE_STATIC_RPM 5
|
||||
|
||||
extern int vega12_thermal_get_temperature(struct pp_hwmgr *hwmgr);
|
||||
extern int vega12_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr);
|
||||
extern int vega12_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
|
||||
struct phm_fan_speed_info *fan_speed_info);
|
||||
extern int vega12_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr);
|
||||
extern int vega12_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr,
|
||||
uint32_t *speed);
|
||||
extern int vega12_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr);
|
||||
extern int vega12_thermal_disable_alert(struct pp_hwmgr *hwmgr);
|
||||
extern int vega12_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr);
|
||||
extern int vega12_start_thermal_controller(struct pp_hwmgr *hwmgr,
|
||||
struct PP_TemperatureRange *range);
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -232,6 +232,20 @@ enum phm_platform_caps {
|
|||
PHM_PlatformCaps_UVDClientMCTuning,
|
||||
PHM_PlatformCaps_ODNinACSupport,
|
||||
PHM_PlatformCaps_ODNinDCSupport,
|
||||
PHM_PlatformCaps_UMDPState,
|
||||
PHM_PlatformCaps_AutoWattmanSupport,
|
||||
PHM_PlatformCaps_AutoWattmanEnable_CCCState,
|
||||
PHM_PlatformCaps_FreeSyncActive,
|
||||
PHM_PlatformCaps_EnableShadowPstate,
|
||||
PHM_PlatformCaps_customThermalManagement,
|
||||
PHM_PlatformCaps_staticFanControl,
|
||||
PHM_PlatformCaps_Virtual_System,
|
||||
PHM_PlatformCaps_LowestUclkReservedForUlv,
|
||||
PHM_PlatformCaps_EnableBoostState,
|
||||
PHM_PlatformCaps_AVFSSupport,
|
||||
PHM_PlatformCaps_ThermalPolicyDelay,
|
||||
PHM_PlatformCaps_CustomFanControlSupport,
|
||||
PHM_PlatformCaps_BAMACO,
|
||||
PHM_PlatformCaps_Max
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -585,6 +585,27 @@ struct phm_ppt_v2_information {
|
|||
uint8_t uc_dcef_dpm_voltage_mode;
|
||||
};
|
||||
|
||||
struct phm_ppt_v3_information
|
||||
{
|
||||
uint8_t uc_thermal_controller_type;
|
||||
|
||||
uint16_t us_small_power_limit1;
|
||||
uint16_t us_small_power_limit2;
|
||||
uint16_t us_boost_power_limit;
|
||||
|
||||
uint16_t us_od_turbo_power_limit;
|
||||
uint16_t us_od_powersave_power_limit;
|
||||
uint16_t us_software_shutdown_temp;
|
||||
|
||||
uint32_t *power_saving_clock_max;
|
||||
uint32_t *power_saving_clock_min;
|
||||
|
||||
uint32_t *od_settings_max;
|
||||
uint32_t *od_settings_min;
|
||||
|
||||
void *smc_pptable;
|
||||
};
|
||||
|
||||
struct phm_dynamic_state_info {
|
||||
struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
|
||||
struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
|
||||
|
|
|
|||
Loading…
Reference in New Issue