spi/rockchip: call wait_for_idle() for the transfer to complete
Suggested-by: Mark Brown <broonie@kernel.org> Signed-off-by: Addy Ke <addy.ke@rockchip.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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@ -214,6 +214,18 @@ static inline void flush_fifo(struct rockchip_spi *rs)
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readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
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}
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static inline void wait_for_idle(struct rockchip_spi *rs)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(5);
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do {
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if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
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return;
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} while (time_before(jiffies, timeout));
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dev_warn(rs->dev, "spi controller is in busy state!\n");
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}
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static u32 get_fifo_len(struct rockchip_spi *rs)
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{
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u32 fifo;
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@ -371,6 +383,10 @@ static int rockchip_spi_pio_transfer(struct rockchip_spi *rs)
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cpu_relax();
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} while (remain);
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/* If tx, wait until the FIFO data completely. */
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if (rs->tx)
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wait_for_idle(rs);
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return 0;
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}
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@ -393,6 +409,9 @@ static void rockchip_spi_dma_txcb(void *data)
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unsigned long flags;
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struct rockchip_spi *rs = data;
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/* Wait until the FIFO data completely. */
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wait_for_idle(rs);
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spin_lock_irqsave(&rs->lock, flags);
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rs->state &= ~TXBUSY;
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@ -536,11 +555,6 @@ static int rockchip_spi_transfer_one(
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rs->tx_sg = xfer->tx_sg;
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rs->rx_sg = xfer->rx_sg;
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/* Delay until the FIFO data completely */
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if (xfer->tx_buf)
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xfer->delay_usecs
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= rs->fifo_len * rs->bpw * 1000000 / rs->speed;
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if (rs->tx && rs->rx)
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rs->tmode = CR0_XFM_TR;
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else if (rs->tx)
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