dt-bindings: net: dsa: realtek-smi: document new compatible rtl8365mb
rtl8365mb is a new realtek-smi subdriver for the RTL8365MB-VC 4+1 port 10/100/1000M Ethernet switch controller. Its compatible string is "realtek,rtl8365mb". Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -9,6 +9,7 @@ SMI-based Realtek devices.
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Required properties:
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- compatible: must be exactly one of:
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"realtek,rtl8365mb" (4+1 ports)
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"realtek,rtl8366"
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"realtek,rtl8366rb" (4+1 ports)
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"realtek,rtl8366s" (4+1 ports)
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@ -62,6 +63,8 @@ and subnodes of DSA switches.
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Examples:
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An example for the RTL8366RB:
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switch {
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compatible = "realtek,rtl8366rb";
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/* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */
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@ -151,3 +154,87 @@ switch {
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};
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};
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};
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An example for the RTL8365MB-VC:
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switch {
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compatible = "realtek,rtl8365mb";
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mdc-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
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mdio-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
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switch_intc: interrupt-controller {
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interrupt-parent = <&gpio5>;
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interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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port@0 {
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reg = <0>;
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label = "swp0";
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phy-handle = <ðphy0>;
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};
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port@1 {
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reg = <1>;
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label = "swp1";
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phy-handle = <ðphy1>;
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};
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port@2 {
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reg = <2>;
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label = "swp2";
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phy-handle = <ðphy2>;
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};
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port@3 {
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reg = <3>;
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label = "swp3";
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phy-handle = <ðphy3>;
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};
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port@6 {
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reg = <6>;
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label = "cpu";
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ethernet = <&fec1>;
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phy-mode = "rgmii";
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tx-internal-delay-ps = <2000>;
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rx-internal-delay-ps = <2000>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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};
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mdio {
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compatible = "realtek,smi-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: phy@0 {
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reg = <0>;
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interrupt-parent = <&switch_intc>;
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interrupts = <0>;
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};
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ethphy1: phy@1 {
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reg = <1>;
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interrupt-parent = <&switch_intc>;
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interrupts = <1>;
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};
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ethphy2: phy@2 {
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reg = <2>;
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interrupt-parent = <&switch_intc>;
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interrupts = <2>;
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};
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ethphy3: phy@3 {
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reg = <3>;
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interrupt-parent = <&switch_intc>;
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interrupts = <3>;
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};
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};
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};
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