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dmaengine: idma64: make better performance on pause / resume 

Accordingly to the documentation the CH_DRAIN bit enforses single bursts when
channel is going to be suspended. This, in case when channel will be resumed,
makes data to flow in non-optimal mode until DMA returns to full burst mode.
The fix differentiates pause / resume cycle from pause / terminate and sets
CH_DRAIN bit accordingly.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Andy Shevchenko 2015-09-14 11:55:40 +03:00 committed by Vinod Koul
parent 581ec089a5
commit 2e9b55becc
1 changed files with 8 additions and 6 deletions
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14
drivers/dma/idma64.c
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@ -65,9 +65,6 @@ static void idma64_chan_init(struct idma64 *idma64, struct idma64_chan *idma64c)
u32 cfghi = IDMA64C_CFGH_SRC_PER(1) | IDMA64C_CFGH_DST_PER(0); u32 cfghi = IDMA64C_CFGH_SRC_PER(1) | IDMA64C_CFGH_DST_PER(0);
u32 cfglo = 0; u32 cfglo = 0;
/* Enforce FIFO drain when channel is suspended */
cfglo |= IDMA64C_CFGL_CH_DRAIN;
/* Set default burst alignment */ /* Set default burst alignment */
cfglo |= IDMA64C_CFGL_DST_BURST_ALIGN | IDMA64C_CFGL_SRC_BURST_ALIGN; cfglo |= IDMA64C_CFGL_DST_BURST_ALIGN | IDMA64C_CFGL_SRC_BURST_ALIGN;
@ -428,12 +425,17 @@ static int idma64_slave_config(struct dma_chan *chan,
return 0; return 0;
} }
static void idma64_chan_deactivate(struct idma64_chan *idma64c) static void idma64_chan_deactivate(struct idma64_chan *idma64c, bool drain)
{ {
unsigned short count = 100; unsigned short count = 100;
u32 cfglo; u32 cfglo;
cfglo = channel_readl(idma64c, CFG_LO); cfglo = channel_readl(idma64c, CFG_LO);
if (drain)
cfglo |= IDMA64C_CFGL_CH_DRAIN;
else
cfglo &= ~IDMA64C_CFGL_CH_DRAIN;
channel_writel(idma64c, CFG_LO, cfglo | IDMA64C_CFGL_CH_SUSP); channel_writel(idma64c, CFG_LO, cfglo | IDMA64C_CFGL_CH_SUSP);
do { do {
udelay(1); udelay(1);
@ -456,7 +458,7 @@ static int idma64_pause(struct dma_chan *chan)
spin_lock_irqsave(&idma64c->vchan.lock, flags); spin_lock_irqsave(&idma64c->vchan.lock, flags);
if (idma64c->desc && idma64c->desc->status == DMA_IN_PROGRESS) { if (idma64c->desc && idma64c->desc->status == DMA_IN_PROGRESS) {
idma64_chan_deactivate(idma64c); idma64_chan_deactivate(idma64c, false);
idma64c->desc->status = DMA_PAUSED; idma64c->desc->status = DMA_PAUSED;
} }
spin_unlock_irqrestore(&idma64c->vchan.lock, flags); spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
@ -486,7 +488,7 @@ static int idma64_terminate_all(struct dma_chan *chan)
LIST_HEAD(head); LIST_HEAD(head);
spin_lock_irqsave(&idma64c->vchan.lock, flags); spin_lock_irqsave(&idma64c->vchan.lock, flags);
idma64_chan_deactivate(idma64c); idma64_chan_deactivate(idma64c, true);
idma64_stop_transfer(idma64c); idma64_stop_transfer(idma64c);
if (idma64c->desc) { if (idma64c->desc) {
idma64_vdesc_free(&idma64c->desc->vdesc); idma64_vdesc_free(&idma64c->desc->vdesc);