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riscv: prefix IRQ_ macro names with an RV_ namespace 

"IRQ_TIMER", used in the arch/riscv CSR header file, is a sufficiently
generic macro name that it's used by several source files across the
Linux code base.  Some of these other files ultimately include the
arch/riscv CSR include file, causing collisions.  Fix by prefixing the
RISC-V csr.h IRQ_ macro names with an RV_ prefix.

Fixes: a4c3733d32 ("riscv: abstract out CSR names for supervisor vs machine mode")
Reported-by: Olof Johansson <olof@lixom.net>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
This commit is contained in:
Paul Walmsley 2019-12-20 03:09:49 -08:00
parent 9d05c18e8d
commit 2f3035da40
3 changed files with 13 additions and 13 deletions
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18
arch/riscv/include/asm/csr.h
View File

@ -116,9 +116,9 @@
# define SR_PIE SR_MPIE # define SR_PIE SR_MPIE
# define SR_PP SR_MPP # define SR_PP SR_MPP
# define IRQ_SOFT IRQ_M_SOFT # define RV_IRQ_SOFT IRQ_M_SOFT
# define IRQ_TIMER IRQ_M_TIMER # define RV_IRQ_TIMER IRQ_M_TIMER
# define IRQ_EXT IRQ_M_EXT # define RV_IRQ_EXT IRQ_M_EXT
#else /* CONFIG_RISCV_M_MODE */ #else /* CONFIG_RISCV_M_MODE */
# define CSR_STATUS CSR_SSTATUS # define CSR_STATUS CSR_SSTATUS
# define CSR_IE CSR_SIE # define CSR_IE CSR_SIE
@ -133,15 +133,15 @@
# define SR_PIE SR_SPIE # define SR_PIE SR_SPIE
# define SR_PP SR_SPP # define SR_PP SR_SPP
# define IRQ_SOFT IRQ_S_SOFT # define RV_IRQ_SOFT IRQ_S_SOFT
# define IRQ_TIMER IRQ_S_TIMER # define RV_IRQ_TIMER IRQ_S_TIMER
# define IRQ_EXT IRQ_S_EXT # define RV_IRQ_EXT IRQ_S_EXT
#endif /* CONFIG_RISCV_M_MODE */ #endif /* CONFIG_RISCV_M_MODE */
/* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */ /* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */
#define IE_SIE (_AC(0x1, UL) << IRQ_SOFT) #define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT)
#define IE_TIE (_AC(0x1, UL) << IRQ_TIMER) #define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER)
#define IE_EIE (_AC(0x1, UL) << IRQ_EXT) #define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT)
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__

6
arch/riscv/kernel/irq.c
View File

@ -23,11 +23,11 @@ asmlinkage __visible void __irq_entry do_IRQ(struct pt_regs *regs)
irq_enter(); irq_enter();
switch (regs->cause & ~CAUSE_IRQ_FLAG) { switch (regs->cause & ~CAUSE_IRQ_FLAG) {
case IRQ_TIMER: case RV_IRQ_TIMER:
riscv_timer_interrupt(); riscv_timer_interrupt();
break; break;
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
case IRQ_SOFT: case RV_IRQ_SOFT:
/* /*
* We only use software interrupts to pass IPIs, so if a non-SMP * We only use software interrupts to pass IPIs, so if a non-SMP
* system gets one, then we don't know what to do. * system gets one, then we don't know what to do.
@ -35,7 +35,7 @@ asmlinkage __visible void __irq_entry do_IRQ(struct pt_regs *regs)
riscv_software_interrupt(); riscv_software_interrupt();
break; break;
#endif #endif
case IRQ_EXT: case RV_IRQ_EXT:
handle_arch_irq(regs); handle_arch_irq(regs);
break; break;
default: default:

2
drivers/irqchip/irq-sifive-plic.c
View File

@ -256,7 +256,7 @@ static int __init plic_init(struct device_node *node,
* Skip contexts other than external interrupts for our * Skip contexts other than external interrupts for our
* privilege level. * privilege level.
*/ */
if (parent.args[0] != IRQ_EXT) if (parent.args[0] != RV_IRQ_EXT)
continue; continue;
hartid = plic_find_hart_id(parent.np); hartid = plic_find_hart_id(parent.np);