arm64: Consolidate CPU Sanity check to CPU Feature infrastructure
This patch consolidates the CPU Sanity check to the new infrastructure. Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Tested-by: Dave Martin <Dave.Martin@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Suzuki K. Poulose
Catalin Marinas
parent
3c739b5710
commit
3086d391f9
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@ -64,6 +64,7 @@ void cpuinfo_store_cpu(void);
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void __init cpuinfo_store_boot_cpu(void);
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void __init init_cpu_features(struct cpuinfo_arm64 *info);
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void update_cpu_features(struct cpuinfo_arm64 *info);
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void update_cpu_features(int cpu, struct cpuinfo_arm64 *info,
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struct cpuinfo_arm64 *boot);
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#endif /* __ASM_CPU_H */
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@ -438,12 +438,9 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info)
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update_mixed_endian_el0_support(info);
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}
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static void update_cpu_ftr_reg(u32 sys_reg, u64 new)
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static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
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{
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struct arm64_ftr_bits *ftrp;
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struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
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BUG_ON(!reg);
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for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
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s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
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@ -458,36 +455,137 @@ static void update_cpu_ftr_reg(u32 sys_reg, u64 new)
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}
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/* Update CPU feature register from non-boot CPU */
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void update_cpu_features(struct cpuinfo_arm64 *info)
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static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
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{
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update_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
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update_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
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update_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
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update_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
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update_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
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update_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
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update_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
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update_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
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update_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
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update_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
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update_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
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update_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
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update_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
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update_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
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update_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
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update_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
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update_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
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update_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
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update_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
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update_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
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update_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
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update_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
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update_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
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update_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
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update_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
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update_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
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update_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
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struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
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BUG_ON(!regp);
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update_cpu_ftr_reg(regp, val);
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if ((boot & regp->strict_mask) == (val & regp->strict_mask))
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return 0;
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pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
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regp->name, boot, cpu, val);
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return 1;
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}
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/*
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* Update system wide CPU feature registers with the values from a
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* non-boot CPU. Also performs SANITY checks to make sure that there
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* aren't any insane variations from that of the boot CPU.
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*/
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void update_cpu_features(int cpu,
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struct cpuinfo_arm64 *info,
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struct cpuinfo_arm64 *boot)
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{
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int taint = 0;
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/*
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* The kernel can handle differing I-cache policies, but otherwise
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* caches should look identical. Userspace JITs will make use of
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* *minLine.
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*/
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taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
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info->reg_ctr, boot->reg_ctr);
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/*
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* Userspace may perform DC ZVA instructions. Mismatched block sizes
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* could result in too much or too little memory being zeroed if a
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* process is preempted and migrated between CPUs.
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*/
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taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
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info->reg_dczid, boot->reg_dczid);
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/* If different, timekeeping will be broken (especially with KVM) */
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taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
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info->reg_cntfrq, boot->reg_cntfrq);
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/*
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* The kernel uses self-hosted debug features and expects CPUs to
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* support identical debug features. We presently need CTX_CMPs, WRPs,
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* and BRPs to be identical.
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* ID_AA64DFR1 is currently RES0.
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*/
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taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
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info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
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taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
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info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
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/*
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* Even in big.LITTLE, processors should be identical instruction-set
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* wise.
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*/
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taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
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info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
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taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
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info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
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/*
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* Differing PARange support is fine as long as all peripherals and
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* memory are mapped within the minimum PARange of all CPUs.
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* Linux should not care about secure memory.
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*/
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taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
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info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
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taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
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info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
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/*
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* EL3 is not our concern.
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* ID_AA64PFR1 is currently RES0.
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*/
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taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
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info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
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taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
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info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
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/*
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* If we have AArch32, we care about 32-bit features for compat. These
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* registers should be RES0 otherwise.
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*/
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taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
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info->reg_id_dfr0, boot->reg_id_dfr0);
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taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
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info->reg_id_isar0, boot->reg_id_isar0);
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taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
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info->reg_id_isar1, boot->reg_id_isar1);
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taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
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info->reg_id_isar2, boot->reg_id_isar2);
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taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
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info->reg_id_isar3, boot->reg_id_isar3);
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taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
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info->reg_id_isar4, boot->reg_id_isar4);
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taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
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info->reg_id_isar5, boot->reg_id_isar5);
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/*
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* Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
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* ACTLR formats could differ across CPUs and therefore would have to
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* be trapped for virtualization anyway.
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*/
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taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
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info->reg_id_mmfr0, boot->reg_id_mmfr0);
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taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
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info->reg_id_mmfr1, boot->reg_id_mmfr1);
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taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
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info->reg_id_mmfr2, boot->reg_id_mmfr2);
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taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
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info->reg_id_mmfr3, boot->reg_id_mmfr3);
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taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
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info->reg_id_pfr0, boot->reg_id_pfr0);
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taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
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info->reg_id_pfr1, boot->reg_id_pfr1);
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taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
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info->reg_mvfr0, boot->reg_mvfr0);
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taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
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info->reg_mvfr1, boot->reg_mvfr1);
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taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
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info->reg_mvfr2, boot->reg_mvfr2);
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/*
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* Mismatched CPU features are a recipe for disaster. Don't even
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* pretend to support them.
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*/
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WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC,
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"Unsupported CPU feature variation.\n");
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update_mixed_endian_el0_support(info);
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}
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@ -192,116 +192,6 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
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pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);
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}
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static int check_reg_mask(char *name, u64 mask, u64 boot, u64 cur, int cpu)
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{
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if ((boot & mask) == (cur & mask))
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return 0;
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pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016lx, CPU%d: %#016lx\n",
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name, (unsigned long)boot, cpu, (unsigned long)cur);
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return 1;
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}
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#define CHECK_MASK(field, mask, boot, cur, cpu) \
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check_reg_mask(#field, mask, (boot)->reg_ ## field, (cur)->reg_ ## field, cpu)
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#define CHECK(field, boot, cur, cpu) \
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CHECK_MASK(field, ~0ULL, boot, cur, cpu)
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/*
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* Verify that CPUs don't have unexpected differences that will cause problems.
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*/
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static void cpuinfo_sanity_check(struct cpuinfo_arm64 *cur)
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{
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unsigned int cpu = smp_processor_id();
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struct cpuinfo_arm64 *boot = &boot_cpu_data;
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unsigned int diff = 0;
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/*
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* The kernel can handle differing I-cache policies, but otherwise
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* caches should look identical. Userspace JITs will make use of
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* *minLine.
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*/
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diff |= CHECK_MASK(ctr, 0xffff3fff, boot, cur, cpu);
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/*
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* Userspace may perform DC ZVA instructions. Mismatched block sizes
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* could result in too much or too little memory being zeroed if a
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* process is preempted and migrated between CPUs.
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*/
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diff |= CHECK(dczid, boot, cur, cpu);
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/* If different, timekeeping will be broken (especially with KVM) */
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diff |= CHECK(cntfrq, boot, cur, cpu);
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/*
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* The kernel uses self-hosted debug features and expects CPUs to
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* support identical debug features. We presently need CTX_CMPs, WRPs,
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* and BRPs to be identical.
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* ID_AA64DFR1 is currently RES0.
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*/
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diff |= CHECK(id_aa64dfr0, boot, cur, cpu);
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diff |= CHECK(id_aa64dfr1, boot, cur, cpu);
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/*
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* Even in big.LITTLE, processors should be identical instruction-set
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* wise.
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*/
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diff |= CHECK(id_aa64isar0, boot, cur, cpu);
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diff |= CHECK(id_aa64isar1, boot, cur, cpu);
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/*
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* Differing PARange support is fine as long as all peripherals and
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* memory are mapped within the minimum PARange of all CPUs.
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* Linux should not care about secure memory.
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* ID_AA64MMFR1 is currently RES0.
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*/
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diff |= CHECK_MASK(id_aa64mmfr0, 0xffffffffffff0ff0, boot, cur, cpu);
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diff |= CHECK(id_aa64mmfr1, boot, cur, cpu);
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/*
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* EL3 is not our concern.
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* ID_AA64PFR1 is currently RES0.
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*/
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diff |= CHECK_MASK(id_aa64pfr0, 0xffffffffffff0fff, boot, cur, cpu);
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diff |= CHECK(id_aa64pfr1, boot, cur, cpu);
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/*
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* If we have AArch32, we care about 32-bit features for compat. These
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* registers should be RES0 otherwise.
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*/
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diff |= CHECK(id_dfr0, boot, cur, cpu);
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diff |= CHECK(id_isar0, boot, cur, cpu);
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diff |= CHECK(id_isar1, boot, cur, cpu);
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diff |= CHECK(id_isar2, boot, cur, cpu);
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diff |= CHECK(id_isar3, boot, cur, cpu);
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diff |= CHECK(id_isar4, boot, cur, cpu);
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diff |= CHECK(id_isar5, boot, cur, cpu);
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/*
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* Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
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* ACTLR formats could differ across CPUs and therefore would have to
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* be trapped for virtualization anyway.
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*/
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diff |= CHECK_MASK(id_mmfr0, 0xff0fffff, boot, cur, cpu);
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diff |= CHECK(id_mmfr1, boot, cur, cpu);
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diff |= CHECK(id_mmfr2, boot, cur, cpu);
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diff |= CHECK(id_mmfr3, boot, cur, cpu);
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diff |= CHECK(id_pfr0, boot, cur, cpu);
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diff |= CHECK(id_pfr1, boot, cur, cpu);
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diff |= CHECK(mvfr0, boot, cur, cpu);
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diff |= CHECK(mvfr1, boot, cur, cpu);
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diff |= CHECK(mvfr2, boot, cur, cpu);
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/*
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* Mismatched CPU features are a recipe for disaster. Don't even
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* pretend to support them.
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*/
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WARN_TAINT_ONCE(diff, TAINT_CPU_OUT_OF_SPEC,
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"Unsupported CPU feature variation.\n");
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}
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static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
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{
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info->reg_cntfrq = arch_timer_get_cntfrq();
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@ -346,8 +236,7 @@ void cpuinfo_store_cpu(void)
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{
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struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
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__cpuinfo_store_cpu(info);
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cpuinfo_sanity_check(info);
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update_cpu_features(info);
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update_cpu_features(smp_processor_id(), info, &boot_cpu_data);
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}
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void __init cpuinfo_store_boot_cpu(void)
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