Pin control fixes for v4.18:
- A slew of driver fixes for Mediatek mt7622 - Fix a direction inversion bug in the Ingenic driver - Fix unsupported drive strength setting on the PFC r8a77970 - Off by one and NULL dereference fixes in the NSP driver -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJbTKXsAAoJEEEQszewGV1ziHgP/jadFt2tdSRYjiF+qT+uxhF6 25oiI0IhOj1Ec8xZ7OkMeUHjYaRFuiustuwXGHailOOWvkGDiVegHXWtv93MqBja TGJKvJHyuJFqmowSvhnHZb9TKgQcn9rjLSEemiHuxt7e64TlUVu7K8yxVUOKkuod ZXTyIiIk7FJaVSm/yg/y0l6KqPgiJMYm5Z71BZFd4c7+HYH01vHLaV2II1d0HH4Z jAvx+z7ueiZ1MPfbIe73Okihj/CtYqN2nk47vZbmiTo9EJxYa9qUhhyLVpv7AE1f mE+Z2o5bH2m1Y4R0RZVjwMJ97jl2rBQJVa/uqssxWEt723/t3qEMMJuh2GaWUYLB AAcT/47Sq0R1JtELDpB4p8558GVZBGlUIKnvtG5+UAPY2xhCYTNr5mmVd2oOgDjI Z39gMWIJuWyDKArce8stRt71UaJLWzh/sgYtIH+KVYCf7rdwe0fR4SkRqDGFwN1s uzQYod8t46c08FZERHgnLgEgoM/QMqVSnTn9JvN9i/SI8YYk9RMFp1XC87g5J50A /NonKGRqR4+wvUtO35Lu2xnTWtuccqxWSf9w9MWqiEK/YONB80+xCyafOL6qjB+C A1xAIl2Mhqp+qBUYVot6ayAEz2CUlA2Rzg5UpKdOMStoHlXkRNWukf7Tn4AgbXaf XbBLFzFv18x4zW7pcrog =Uloq -----END PGP SIGNATURE----- Merge tag 'pinctrl-v4.18-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control fixes from Linus Walleij: - A slew of driver fixes for Mediatek mt7622 - Fix a direction inversion bug in the Ingenic driver - Fix unsupported drive strength setting on the PFC r8a77970 - Off by one and NULL dereference fixes in the NSP driver * tag 'pinctrl-v4.18-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: nsp: Fix potential NULL dereference pinctrl: nsp: off by ones in nsp_pinmux_enable() pinctrl: sh-pfc: r8a77970: remove SH_PFC_PIN_CFG_DRIVE_STRENGTH flag pinctrl: ingenic: Fix inverted direction for < JZ4770 pinctrl: mt7622: fix a kernel panic when gpio-hog is being applied pinctrl: mt7622: stop using the deprecated pinctrl_add_gpio_range pinctrl: mt7622: fix that pinctrl_claim_hogs cannot work pinctrl: mt7622: fix initialization sequence between eint and gpiochip pinctrl: mt7622: fix error path on failing at groups building
This commit is contained in:
Linus Torvalds
commit
30b06abfb9
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@ -460,8 +460,8 @@ static int nsp_pinmux_enable(struct pinctrl_dev *pctrl_dev,
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const struct nsp_pin_function *func;
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const struct nsp_pin_group *grp;
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if (grp_select > pinctrl->num_groups ||
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func_select > pinctrl->num_functions)
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if (grp_select >= pinctrl->num_groups ||
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func_select >= pinctrl->num_functions)
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return -EINVAL;
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func = &pinctrl->functions[func_select];
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@ -577,6 +577,8 @@ static int nsp_pinmux_probe(struct platform_device *pdev)
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return PTR_ERR(pinctrl->base0);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!res)
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return -EINVAL;
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pinctrl->base1 = devm_ioremap_nocache(&pdev->dev, res->start,
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resource_size(res));
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if (!pinctrl->base1) {
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@ -1424,7 +1424,7 @@ static struct pinctrl_desc mtk_desc = {
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static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
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{
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struct mtk_pinctrl *hw = dev_get_drvdata(chip->parent);
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struct mtk_pinctrl *hw = gpiochip_get_data(chip);
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int value, err;
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err = mtk_hw_get_value(hw, gpio, PINCTRL_PIN_REG_DI, &value);
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@ -1436,7 +1436,7 @@ static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
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static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
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{
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struct mtk_pinctrl *hw = dev_get_drvdata(chip->parent);
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struct mtk_pinctrl *hw = gpiochip_get_data(chip);
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mtk_hw_set_value(hw, gpio, PINCTRL_PIN_REG_DO, !!value);
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}
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@ -1508,11 +1508,20 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
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if (ret < 0)
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return ret;
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ret = gpiochip_add_pin_range(chip, dev_name(hw->dev), 0, 0,
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chip->ngpio);
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if (ret < 0) {
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gpiochip_remove(chip);
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return ret;
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/* Just for backward compatible for these old pinctrl nodes without
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* "gpio-ranges" property. Otherwise, called directly from a
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* DeviceTree-supported pinctrl driver is DEPRECATED.
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* Please see Section 2.1 of
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* Documentation/devicetree/bindings/gpio/gpio.txt on how to
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* bind pinctrl and gpio drivers via the "gpio-ranges" property.
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*/
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if (!of_find_property(np, "gpio-ranges", NULL)) {
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ret = gpiochip_add_pin_range(chip, dev_name(hw->dev), 0, 0,
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chip->ngpio);
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if (ret < 0) {
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gpiochip_remove(chip);
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return ret;
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}
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}
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return 0;
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@ -1695,15 +1704,16 @@ static int mtk_pinctrl_probe(struct platform_device *pdev)
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mtk_desc.custom_conf_items = mtk_conf_items;
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#endif
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hw->pctrl = devm_pinctrl_register(&pdev->dev, &mtk_desc, hw);
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if (IS_ERR(hw->pctrl))
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return PTR_ERR(hw->pctrl);
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err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
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&hw->pctrl);
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if (err)
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return err;
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/* Setup groups descriptions per SoC types */
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err = mtk_build_groups(hw);
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if (err) {
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dev_err(&pdev->dev, "Failed to build groups\n");
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return 0;
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return err;
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}
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/* Setup functions descriptions per SoC types */
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@ -1713,17 +1723,25 @@ static int mtk_pinctrl_probe(struct platform_device *pdev)
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return err;
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}
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err = mtk_build_gpiochip(hw, pdev->dev.of_node);
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if (err) {
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dev_err(&pdev->dev, "Failed to add gpio_chip\n");
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/* For able to make pinctrl_claim_hogs, we must not enable pinctrl
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* until all groups and functions are being added one.
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*/
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err = pinctrl_enable(hw->pctrl);
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if (err)
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return err;
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}
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err = mtk_build_eint(hw, pdev);
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if (err)
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dev_warn(&pdev->dev,
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"Failed to add EINT, but pinctrl still can work\n");
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/* Build gpiochip should be after pinctrl_enable is done */
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err = mtk_build_gpiochip(hw, pdev->dev.of_node);
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if (err) {
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dev_err(&pdev->dev, "Failed to add gpio_chip\n");
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return err;
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}
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platform_set_drvdata(pdev, hw);
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return 0;
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@ -536,7 +536,7 @@ static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
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ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);
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} else {
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ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false);
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ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, input);
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ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input);
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ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false);
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}
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@ -21,15 +21,13 @@
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#include "core.h"
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#include "sh_pfc.h"
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#define CFG_FLAGS SH_PFC_PIN_CFG_DRIVE_STRENGTH
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#define CPU_ALL_PORT(fn, sfx) \
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PORT_GP_CFG_22(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
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PORT_GP_CFG_17(2, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_17(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_6(4, fn, sfx, CFG_FLAGS), \
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PORT_GP_CFG_15(5, fn, sfx, CFG_FLAGS)
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PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_28(1, fn, sfx), \
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PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_6(4, fn, sfx), \
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PORT_GP_15(5, fn, sfx)
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/*
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* F_() : just information
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* FM() : macro for FN_xxx / xxx_MARK
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