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drm/tegra: sor: Make XBAR configurable per SoC 

Provide a per-SoC mapping of lanes which can be used to configure the
XBAR.

Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding 2015-08-03 15:50:32 +02:00
parent 618dee3941
commit 30b4943558
1 changed files with 28 additions and 13 deletions
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41
drivers/gpu/drm/tegra/sor.c
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@ -151,6 +151,8 @@ struct tegra_sor_soc {
const struct tegra_sor_hdmi_settings *settings;
unsigned int num_settings;
const u8 *xbar_cfg;
};
struct tegra_sor;
@ -1613,6 +1615,14 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder)
value &= ~SOR_PLL2_PORT_POWERDOWN;
tegra_sor_writel(sor, value, SOR_PLL2);
/* XXX not in TRM */
for (value = 0, i = 0; i < 5; i++)
value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
SOR_XBAR_CTRL_LINK1_XSEL(i, i);
tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
/* switch to DP parent clock */
err = tegra_sor_set_parent_clock(sor, sor->clk_dp);
if (err < 0)
@ -1980,7 +1990,7 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
struct tegra_sor *sor = to_sor(output);
struct tegra_sor_state *state;
struct drm_display_mode *mode;
unsigned int div;
unsigned int div, i;
u32 value;
int err;
@ -2086,20 +2096,13 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
tegra_sor_writel(sor, value, SOR_REFCLK);
/* XXX don't hardcode */
value = SOR_XBAR_CTRL_LINK1_XSEL(4, 4) |
SOR_XBAR_CTRL_LINK1_XSEL(3, 3) |
SOR_XBAR_CTRL_LINK1_XSEL(2, 2) |
SOR_XBAR_CTRL_LINK1_XSEL(1, 1) |
SOR_XBAR_CTRL_LINK1_XSEL(0, 0) |
SOR_XBAR_CTRL_LINK0_XSEL(4, 4) |
SOR_XBAR_CTRL_LINK0_XSEL(3, 3) |
SOR_XBAR_CTRL_LINK0_XSEL(2, 0) |
SOR_XBAR_CTRL_LINK0_XSEL(1, 1) |
SOR_XBAR_CTRL_LINK0_XSEL(0, 2);
tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
/* XXX not in TRM */
for (value = 0, i = 0; i < 5; i++)
value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
SOR_XBAR_CTRL_LINK1_XSEL(i, i);
tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
/* switch to parent clock */
err = clk_set_parent(sor->clk_src, sor->clk_parent);
@ -2475,11 +2478,16 @@ static const struct tegra_sor_ops tegra_sor_hdmi_ops = {
.remove = tegra_sor_hdmi_remove,
};
static const u8 tegra124_sor_xbar_cfg[5] = {
0, 1, 2, 3, 4
};
static const struct tegra_sor_soc tegra124_sor = {
.supports_edp = true,
.supports_lvds = true,
.supports_hdmi = false,
.supports_dp = false,
.xbar_cfg = tegra124_sor_xbar_cfg,
};
static const struct tegra_sor_soc tegra210_sor = {
@ -2487,6 +2495,11 @@ static const struct tegra_sor_soc tegra210_sor = {
.supports_lvds = false,
.supports_hdmi = false,
.supports_dp = false,
.xbar_cfg = tegra124_sor_xbar_cfg,
};
static const u8 tegra210_sor_xbar_cfg[5] = {
2, 1, 0, 3, 4
};
static const struct tegra_sor_soc tegra210_sor1 = {
@ -2497,6 +2510,8 @@ static const struct tegra_sor_soc tegra210_sor1 = {
.num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
.settings = tegra210_sor_hdmi_defaults,
.xbar_cfg = tegra210_sor_xbar_cfg,
};
static const struct of_device_id tegra_sor_of_match[] = {