SoCFPGA DTS updates for v4.13
- Fix clocks node the EMACs - VINING board updtes - Remove I2C EEPROMs and LED node - Add QSPI device - Add 2nd ethernet alias - Add 'clock-frequency' binding for i2c node -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJZTSdFAAoJEBmUBAuBoyj0eYcP/2ptr68NC796MXyErFlmLxq5 epFhEdgyALngSGaXHdbZJDjk8VWPA2Ua9H/6xIGVrm9tUc4BVSHECR5XSXVdRI3f XUJHBW1K88l74ghffVHaW9IGts8mcNWEhttjEA1qnhyF/qjQu6KZx6tl/xKCvKCa TEl/UvpJPiu0M/tzHepQ5J7p2LYsS/vR3N4wouuGEfWlD/DTDdadoaiyg7RlFBvj fBoIFr+vzGgBN8HBNQJCcrCG7XhLHzrvw1EWWMNTzVV73IbYz9w4btouZ+FVoJOu Bjs7MAX+A8UW0Wy3gHTTc3Awp9ZF276WxGdcztxciEiZqXmnSyCE3mop8PrH1mij BypI38c23t1r0xluSRYWCXF0S4zEV37dug8HXhmjqcEBj7RXeg+IAfQ+UaKI8XvP NuFDKd9YsN7Vc1GIIIksm2v9/qzZbjV37PiLq4HNdMA0VaFi0i9hskqXuA9bsNn7 cycybu46EyxYjjSP5mJuGjZb6MXdcDMSHLTQWwiYllNb5hVUA3zYv7XvSmFRM22n 73Gt2KBlgxSCtIyMx+vMDXXevPE3l8f4w9yeEk4Av5tv0F8sf5T/iCGdBX9E64Eo Y6OAVNoE4/W4DJasGySzy/Di0+rHTOcRNVzkOmJaqNzIfo2IQ0MghZdInkDvZdIW neklhVn5pOIelPDrldjq =cknj -----END PGP SIGNATURE----- Merge tag 'socfpga_dts_for_v4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt Pull "SoCFPGA DTS updates for v4.13" from Dinh Nguyen: - Fix clocks node the EMACs - VINING board updtes - Remove I2C EEPROMs and LED node - Add QSPI device - Add 2nd ethernet alias - Add 'clock-frequency' binding for i2c node * tag 'socfpga_dts_for_v4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: dts: socfpga: set the i2c frequency ARM: dts: socfpga: Add second ethernet alias to VINING FPGA ARM: dts: socfpga: Drop LED node from VINING FPGA ARM: dts: socfpga: Remove I2C EEPROMs from VINING FPGA ARM: dts: socfpga: Enable QSPI support on VINING FPGA ARM: dts: socfpga: Fix the ethernet clock phandle
This commit is contained in:
commit
30e3224e4a
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@ -557,7 +557,7 @@ gmac0: ethernet@ff700000 {
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interrupts = <0 115 4>;
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interrupt-names = "macirq";
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mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
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clocks = <&emac0_clk>;
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clocks = <&emac_0_clk>;
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clock-names = "stmmaceth";
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resets = <&rst EMAC0_RESET>;
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reset-names = "stmmaceth";
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@ -575,7 +575,7 @@ gmac1: ethernet@ff702000 {
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interrupts = <0 120 4>;
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interrupt-names = "macirq";
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mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
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clocks = <&emac1_clk>;
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clocks = <&emac_1_clk>;
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clock-names = "stmmaceth";
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resets = <&rst EMAC1_RESET>;
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reset-names = "stmmaceth";
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@ -130,13 +130,13 @@ a10sr_rst: reset-controller {
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};
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&i2c1 {
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speed-mode = <0>;
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status = "okay";
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/*
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* adjust the falling times to decrease the i2c frequency to 50Khz
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* because the LCD module does not work at the standard 100Khz
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*/
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clock-frequency = <100000>;
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i2c-sda-falling-time-ns = <6000>;
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i2c-scl-falling-time-ns = <6000>;
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@ -86,7 +86,7 @@ &gpio2 {
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&i2c0 {
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status = "okay";
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speed-mode = <0>;
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clock-frequency = <100000>;
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adxl345: adxl345@0 {
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compatible = "adi,adxl345";
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@ -58,7 +58,7 @@ &gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */
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&i2c0 {
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status = "okay";
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speed-mode = <0>;
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clock-frequency = <100000>;
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stmpe1: stmpe811@41 {
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compatible = "st,stmpe811";
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@ -69,34 +69,7 @@ aliases {
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* to be added to the gmac1 device tree blob.
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*/
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ethernet0 = &gmac1;
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};
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leds {
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compatible = "gpio-leds";
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hps_led0 {
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label = "hps:green:led0"; /* ALIVE_LED_GR */
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gpios = <&portb 19 0>; /* HPS_GPIO48 */
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linux,default-trigger = "heartbeat";
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};
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hps_led1 {
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label = "hps:red:led0"; /* ALIVE_LED_RD */
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gpios = <&portb 24 0>; /* HPS_GPIO53 */
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linux,default-trigger = "none";
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};
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hps_led2 {
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label = "hps:green:led1"; /* LINK2HOST_LED_GR */
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gpios = <&portb 25 0>; /* HPS_GPIO54 */
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linux,default-trigger = "heartbeat";
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};
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hps_led3 {
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label = "hps:red:led1"; /* LINK2HOST_LED_RD */
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gpios = <&portc 7 0>; /* HPS_GPIO65 */
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linux,default-trigger = "none";
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};
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ethernet1 = &gmac0;
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};
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gpio-keys {
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@ -203,69 +176,39 @@ i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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eeprom@51 {
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compatible = "at,24c01";
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pagesize = <8>;
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reg = <0x51>;
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};
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};
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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eeprom@51 {
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compatible = "at,24c01";
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pagesize = <8>;
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reg = <0x51>;
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};
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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eeprom@51 {
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compatible = "at,24c01";
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pagesize = <8>;
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reg = <0x51>;
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};
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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eeprom@51 {
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compatible = "at,24c01";
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pagesize = <8>;
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reg = <0x51>;
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};
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};
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i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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eeprom@51 {
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compatible = "at,24c01";
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pagesize = <8>;
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reg = <0x51>;
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};
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};
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i2c@5 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <5>;
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eeprom@51 {
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compatible = "at,24c01";
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pagesize = <8>;
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reg = <0x51>;
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};
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};
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i2c@6 {
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i2c@6 { /* Backplane EEPROM */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <6>;
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@ -276,7 +219,7 @@ eeprom@51 {
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};
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};
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i2c@7 {
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i2c@7 { /* Power board EEPROM */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <7>;
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@ -300,6 +243,44 @@ at24@50 {
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};
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};
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&qspi {
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status = "okay";
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n25q128@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "n25q128";
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reg = <0>; /* chip select */
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spi-max-frequency = <100000000>;
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m25p,fast-read;
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cdns,page-size = <256>;
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cdns,block-size = <16>;
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cdns,read-delay = <4>;
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cdns,tshsl-ns = <50>;
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cdns,tsd2d-ns = <50>;
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cdns,tchsh-ns = <4>;
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cdns,tslch-ns = <4>;
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};
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n25q00@1 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "n25q00";
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reg = <1>; /* chip select */
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spi-max-frequency = <100000000>;
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m25p,fast-read;
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cdns,page-size = <256>;
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cdns,block-size = <16>;
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cdns,read-delay = <4>;
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cdns,tshsl-ns = <50>;
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cdns,tsd2d-ns = <50>;
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cdns,tchsh-ns = <4>;
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cdns,tslch-ns = <4>;
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};
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};
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&usb0 {
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dr_mode = "host";
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status = "okay";
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