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scsi: gdth: remove ISA and EISA support 

The non-PCI code has bitrotted for quite a while and will just oops
on load because it passes a NULL pointer to the PCI DMA routines.

Lets kill it for good - if someone really wants to use one of these
cards I'll help mentoring them to write a proper driver glue.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Christoph Hellwig 2018-12-12 08:41:21 +01:00 committed by Martin K. Petersen
parent 463563fa74
commit 314814552a
3 changed files with 24 additions and 717 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/scsi/Kconfig
View File

@ -665,7 +665,7 @@ config SCSI_DMX3191D
config SCSI_GDTH config SCSI_GDTH
tristate "Intel/ICP (former GDT SCSI Disk Array) RAID Controller support" tristate "Intel/ICP (former GDT SCSI Disk Array) RAID Controller support"
depends on (ISA || EISA || PCI) && SCSI && ISA_DMA_API depends on PCI && SCSI
---help--- ---help---
Formerly called GDT SCSI Disk Array Controller Support. Formerly called GDT SCSI Disk Array Controller Support.

709
drivers/scsi/gdth.c
View File

@ -1,6 +1,6 @@
/************************************************************************ /************************************************************************
* Linux driver for * * Linux driver for *
* ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers * * ICP vortex GmbH: GDT PCI Disk Array Controllers *
* Intel Corporation: Storage RAID Controllers * * Intel Corporation: Storage RAID Controllers *
* * * *
* gdth.c * * gdth.c *
@ -32,15 +32,10 @@
************************************************************************/ ************************************************************************/
/* All GDT Disk Array Controllers are fully supported by this driver. /* All GDT Disk Array Controllers are fully supported by this driver.
* This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the * This includes the PCI SCSI Disk Array Controllers and the
* PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
* list of all controller types. * list of all controller types.
* *
* If you have one or more GDT3000/3020 EISA controllers with
* controller BIOS disabled, you have to set the IRQ values with the
* command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
* the IRQ values for the EISA controllers.
*
* After the optional list of IRQ values, other possible * After the optional list of IRQ values, other possible
* command line options are: * command line options are:
* disable:Y disable driver * disable:Y disable driver
@ -61,14 +56,12 @@
* access a shared resource from several nodes, * access a shared resource from several nodes,
* appropriate controller firmware required * appropriate controller firmware required
* shared_access:N enable driver reserve/release protocol * shared_access:N enable driver reserve/release protocol
* probe_eisa_isa:Y scan for EISA/ISA controllers
* probe_eisa_isa:N do not scan for EISA/ISA controllers
* force_dma32:Y use only 32 bit DMA mode * force_dma32:Y use only 32 bit DMA mode
* force_dma32:N use 64 bit DMA mode, if supported * force_dma32:N use 64 bit DMA mode, if supported
* *
* The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N, * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
* max_ids:127,rescan:N,hdr_channel:0, * max_ids:127,rescan:N,hdr_channel:0,
* shared_access:Y,probe_eisa_isa:N,force_dma32:N". * shared_access:Y,force_dma32:N".
* Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y". * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
* *
* When loading the gdth driver as a module, the same options are available. * When loading the gdth driver as a module, the same options are available.
@ -79,7 +72,7 @@
* *
* Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0 * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
* max_ids=127 rescan=0 hdr_channel=0 shared_access=0 * max_ids=127 rescan=0 hdr_channel=0 shared_access=0
* probe_eisa_isa=0 force_dma32=0" * force_dma32=0"
* The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1". * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
*/ */
@ -286,12 +279,6 @@ static struct timer_list gdth_timer;
#define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b)) #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
#ifdef CONFIG_ISA
static u8 gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
#endif
#if defined(CONFIG_EISA) || defined(CONFIG_ISA)
static u8 gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
#endif
static u8 gdth_polling; /* polling if TRUE */ static u8 gdth_polling; /* polling if TRUE */
static int gdth_ctr_count = 0; /* controller count */ static int gdth_ctr_count = 0; /* controller count */
static LIST_HEAD(gdth_instances); /* controller list */ static LIST_HEAD(gdth_instances); /* controller list */
@ -325,10 +312,6 @@ static u8 gdth_direction_tab[0x100] = {
}; };
/* LILO and modprobe/insmod parameters */ /* LILO and modprobe/insmod parameters */
/* IRQ list for GDT3000/3020 EISA controllers */
static int irq[MAXHA] __initdata =
{0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
/* disable driver flag */ /* disable driver flag */
static int disable __initdata = 0; static int disable __initdata = 0;
/* reserve flag */ /* reserve flag */
@ -348,13 +331,10 @@ static int max_ids = MAXID;
static int rescan = 0; static int rescan = 0;
/* shared access */ /* shared access */
static int shared_access = 1; static int shared_access = 1;
/* enable support for EISA and ISA controllers */
static int probe_eisa_isa = 0;
/* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */ /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
static int force_dma32 = 0; static int force_dma32 = 0;
/* parameters for modprobe/insmod */ /* parameters for modprobe/insmod */
module_param_hw_array(irq, int, irq, NULL, 0);
module_param(disable, int, 0); module_param(disable, int, 0);
module_param(reserve_mode, int, 0); module_param(reserve_mode, int, 0);
module_param_array(reserve_list, int, NULL, 0); module_param_array(reserve_list, int, NULL, 0);
@ -363,7 +343,6 @@ module_param(hdr_channel, int, 0);
module_param(max_ids, int, 0); module_param(max_ids, int, 0);
module_param(rescan, int, 0); module_param(rescan, int, 0);
module_param(shared_access, int, 0); module_param(shared_access, int, 0);
module_param(probe_eisa_isa, int, 0);
module_param(force_dma32, int, 0); module_param(force_dma32, int, 0);
MODULE_AUTHOR("Achim Leubner"); MODULE_AUTHOR("Achim Leubner");
MODULE_LICENSE("GPL"); MODULE_LICENSE("GPL");
@ -515,45 +494,6 @@ static void gdth_eval_mapping(u32 size, u32 *cyls, int *heads, int *secs)
} }
} }
/* controller search and initialization functions */
#ifdef CONFIG_EISA
static int __init gdth_search_eisa(u16 eisa_adr)
{
u32 id;
TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
id = inl(eisa_adr+ID0REG);
if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
if ((inb(eisa_adr+EISAREG) & 8) == 0)
return 0; /* not EISA configured */
return 1;
}
if (id == GDT3_ID) /* GDT3000 */
return 1;
return 0;
}
#endif /* CONFIG_EISA */
#ifdef CONFIG_ISA
static int __init gdth_search_isa(u32 bios_adr)
{
void __iomem *addr;
u32 id;
TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(u32))) != NULL) {
id = readl(addr);
iounmap(addr);
if (id == GDT2_ID) /* GDT2000 */
return 1;
}
return 0;
}
#endif /* CONFIG_ISA */
#ifdef CONFIG_PCI
static bool gdth_search_vortex(u16 device) static bool gdth_search_vortex(u16 device)
{ {
if (device <= PCI_DEVICE_ID_VORTEX_GDT6555) if (device <= PCI_DEVICE_ID_VORTEX_GDT6555)
@ -656,204 +596,7 @@ static int gdth_pci_init_one(struct pci_dev *pdev,
return 0; return 0;
} }
#endif /* CONFIG_PCI */
#ifdef CONFIG_EISA
static int __init gdth_init_eisa(u16 eisa_adr,gdth_ha_str *ha)
{
u32 retries,id;
u8 prot_ver,eisacf,i,irq_found;
TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
/* disable board interrupts, deinitialize services */
outb(0xff,eisa_adr+EDOORREG);
outb(0x00,eisa_adr+EDENABREG);
outb(0x00,eisa_adr+EINTENABREG);
outb(0xff,eisa_adr+LDOORREG);
retries = INIT_RETRIES;
gdth_delay(20);
while (inb(eisa_adr+EDOORREG) != 0xff) {
if (--retries == 0) {
printk("GDT-EISA: Initialization error (DEINIT failed)\n");
return 0;
}
gdth_delay(1);
TRACE2(("wait for DEINIT: retries=%d\n",retries));
}
prot_ver = inb(eisa_adr+MAILBOXREG);
outb(0xff,eisa_adr+EDOORREG);
if (prot_ver != PROTOCOL_VERSION) {
printk("GDT-EISA: Illegal protocol version\n");
return 0;
}
ha->bmic = eisa_adr;
ha->brd_phys = (u32)eisa_adr >> 12;
outl(0,eisa_adr+MAILBOXREG);
outl(0,eisa_adr+MAILBOXREG+4);
outl(0,eisa_adr+MAILBOXREG+8);
outl(0,eisa_adr+MAILBOXREG+12);
/* detect IRQ */
if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
ha->oem_id = OEM_ID_ICP;
ha->type = GDT_EISA;
ha->stype = id;
outl(1,eisa_adr+MAILBOXREG+8);
outb(0xfe,eisa_adr+LDOORREG);
retries = INIT_RETRIES;
gdth_delay(20);
while (inb(eisa_adr+EDOORREG) != 0xfe) {
if (--retries == 0) {
printk("GDT-EISA: Initialization error (get IRQ failed)\n");
return 0;
}
gdth_delay(1);
}
ha->irq = inb(eisa_adr+MAILBOXREG);
outb(0xff,eisa_adr+EDOORREG);
TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
/* check the result */
if (ha->irq == 0) {
TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
for (i = 0, irq_found = FALSE;
i < MAXHA && irq[i] != 0xff; ++i) {
if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
irq_found = TRUE;
break;
}
}
if (irq_found) {
ha->irq = irq[i];
irq[i] = 0;
printk("GDT-EISA: Can not detect controller IRQ,\n");
printk("Use IRQ setting from command line (IRQ = %d)\n",
ha->irq);
} else {
printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
printk("the controller BIOS or use command line parameters\n");
return 0;
}
}
} else {
eisacf = inb(eisa_adr+EISAREG) & 7;
if (eisacf > 4) /* level triggered */
eisacf -= 4;
ha->irq = gdth_irq_tab[eisacf];
ha->oem_id = OEM_ID_ICP;
ha->type = GDT_EISA;
ha->stype = id;
}
ha->dma64_support = 0;
return 1;
}
#endif /* CONFIG_EISA */
#ifdef CONFIG_ISA
static int __init gdth_init_isa(u32 bios_adr,gdth_ha_str *ha)
{
register gdt2_dpram_str __iomem *dp2_ptr;
int i;
u8 irq_drq,prot_ver;
u32 retries;
TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
if (ha->brd == NULL) {
printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
return 0;
}
dp2_ptr = ha->brd;
writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
/* reset interface area */
memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
if (readl(&dp2_ptr->u) != 0) {
printk("GDT-ISA: Initialization error (DPMEM write error)\n");
iounmap(ha->brd);
return 0;
}
/* disable board interrupts, read DRQ and IRQ */
writeb(0xff, &dp2_ptr->io.irqdel);
writeb(0x00, &dp2_ptr->io.irqen);
writeb(0x00, &dp2_ptr->u.ic.S_Status);
writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
irq_drq = readb(&dp2_ptr->io.rq);
for (i=0; i<3; ++i) {
if ((irq_drq & 1)==0)
break;
irq_drq >>= 1;
}
ha->drq = gdth_drq_tab[i];
irq_drq = readb(&dp2_ptr->io.rq) >> 3;
for (i=1; i<5; ++i) {
if ((irq_drq & 1)==0)
break;
irq_drq >>= 1;
}
ha->irq = gdth_irq_tab[i];
/* deinitialize services */
writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
writeb(0, &dp2_ptr->io.event);
retries = INIT_RETRIES;
gdth_delay(20);
while (readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
if (--retries == 0) {
printk("GDT-ISA: Initialization error (DEINIT failed)\n");
iounmap(ha->brd);
return 0;
}
gdth_delay(1);
}
prot_ver = (u8)readl(&dp2_ptr->u.ic.S_Info[0]);
writeb(0, &dp2_ptr->u.ic.Status);
writeb(0xff, &dp2_ptr->io.irqdel);
if (prot_ver != PROTOCOL_VERSION) {
printk("GDT-ISA: Illegal protocol version\n");
iounmap(ha->brd);
return 0;
}
ha->oem_id = OEM_ID_ICP;
ha->type = GDT_ISA;
ha->ic_all_size = sizeof(dp2_ptr->u);
ha->stype= GDT2_ID;
ha->brd_phys = bios_adr >> 4;
/* special request to controller BIOS */
writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
writeb(0, &dp2_ptr->io.event);
retries = INIT_RETRIES;
gdth_delay(20);
while (readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
if (--retries == 0) {
printk("GDT-ISA: Initialization error\n");
iounmap(ha->brd);
return 0;
}
gdth_delay(1);
}
writeb(0, &dp2_ptr->u.ic.Status);
writeb(0xff, &dp2_ptr->io.irqdel);
ha->dma64_support = 0;
return 1;
}
#endif /* CONFIG_ISA */
#ifdef CONFIG_PCI
static int gdth_init_pci(struct pci_dev *pdev, gdth_pci_str *pcistr, static int gdth_init_pci(struct pci_dev *pdev, gdth_pci_str *pcistr,
gdth_ha_str *ha) gdth_ha_str *ha)
{ {
@ -1228,30 +971,19 @@ static int gdth_init_pci(struct pci_dev *pdev, gdth_pci_str *pcistr,
return 1; return 1;
} }
#endif /* CONFIG_PCI */
/* controller protocol functions */ /* controller protocol functions */
static void gdth_enable_int(gdth_ha_str *ha) static void gdth_enable_int(gdth_ha_str *ha)
{ {
unsigned long flags; unsigned long flags;
gdt2_dpram_str __iomem *dp2_ptr;
gdt6_dpram_str __iomem *dp6_ptr; gdt6_dpram_str __iomem *dp6_ptr;
gdt6m_dpram_str __iomem *dp6m_ptr; gdt6m_dpram_str __iomem *dp6m_ptr;
TRACE(("gdth_enable_int() hanum %d\n",ha->hanum)); TRACE(("gdth_enable_int() hanum %d\n",ha->hanum));
spin_lock_irqsave(&ha->smp_lock, flags); spin_lock_irqsave(&ha->smp_lock, flags);
if (ha->type == GDT_EISA) { if (ha->type == GDT_PCI) {
outb(0xff, ha->bmic + EDOORREG);
outb(0xff, ha->bmic + EDENABREG);
outb(0x01, ha->bmic + EINTENABREG);
} else if (ha->type == GDT_ISA) {
dp2_ptr = ha->brd;
writeb(1, &dp2_ptr->io.irqdel);
writeb(0, &dp2_ptr->u.ic.Cmd_Index);
writeb(1, &dp2_ptr->io.irqen);
} else if (ha->type == GDT_PCI) {
dp6_ptr = ha->brd; dp6_ptr = ha->brd;
writeb(1, &dp6_ptr->io.irqdel); writeb(1, &dp6_ptr->io.irqdel);
writeb(0, &dp6_ptr->u.ic.Cmd_Index); writeb(0, &dp6_ptr->u.ic.Cmd_Index);
@ -1275,12 +1007,7 @@ static u8 gdth_get_status(gdth_ha_str *ha)
TRACE(("gdth_get_status() irq %d ctr_count %d\n", ha->irq, gdth_ctr_count)); TRACE(("gdth_get_status() irq %d ctr_count %d\n", ha->irq, gdth_ctr_count));
if (ha->type == GDT_EISA) if (ha->type == GDT_PCI)
IStatus = inb((u16)ha->bmic + EDOORREG);
else if (ha->type == GDT_ISA)
IStatus =
readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
else if (ha->type == GDT_PCI)
IStatus = IStatus =
readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index); readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
else if (ha->type == GDT_PCINEW) else if (ha->type == GDT_PCINEW)
@ -1298,11 +1025,7 @@ static int gdth_test_busy(gdth_ha_str *ha)
TRACE(("gdth_test_busy() hanum %d\n", ha->hanum)); TRACE(("gdth_test_busy() hanum %d\n", ha->hanum));
if (ha->type == GDT_EISA) if (ha->type == GDT_PCI)
gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
else if (ha->type == GDT_ISA)
gdtsema0 = (int)readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
else if (ha->type == GDT_PCI)
gdtsema0 = (int)readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0); gdtsema0 = (int)readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
else if (ha->type == GDT_PCINEW) else if (ha->type == GDT_PCINEW)
gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg)); gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
@ -1336,11 +1059,7 @@ static void gdth_set_sema0(gdth_ha_str *ha)
{ {
TRACE(("gdth_set_sema0() hanum %d\n", ha->hanum)); TRACE(("gdth_set_sema0() hanum %d\n", ha->hanum));
if (ha->type == GDT_EISA) { if (ha->type == GDT_PCI) {
outb(1, ha->bmic + SEMA0REG);
} else if (ha->type == GDT_ISA) {
writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
} else if (ha->type == GDT_PCI) {
writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0); writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
} else if (ha->type == GDT_PCINEW) { } else if (ha->type == GDT_PCINEW) {
outb(1, PTR2USHORT(&ha->plx->sema0_reg)); outb(1, PTR2USHORT(&ha->plx->sema0_reg));
@ -1356,7 +1075,6 @@ static void gdth_copy_command(gdth_ha_str *ha)
register gdt6m_dpram_str __iomem *dp6m_ptr; register gdt6m_dpram_str __iomem *dp6m_ptr;
register gdt6c_dpram_str __iomem *dp6c_ptr; register gdt6c_dpram_str __iomem *dp6c_ptr;
gdt6_dpram_str __iomem *dp6_ptr; gdt6_dpram_str __iomem *dp6_ptr;
gdt2_dpram_str __iomem *dp2_ptr;
u16 cp_count,dp_offset,cmd_no; u16 cp_count,dp_offset,cmd_no;
TRACE(("gdth_copy_command() hanum %d\n", ha->hanum)); TRACE(("gdth_copy_command() hanum %d\n", ha->hanum));
@ -1367,8 +1085,6 @@ static void gdth_copy_command(gdth_ha_str *ha)
cmd_ptr = ha->pccb; cmd_ptr = ha->pccb;
++ha->cmd_cnt; ++ha->cmd_cnt;
if (ha->type == GDT_EISA)
return; /* no DPMEM, no copy */
/* set cpcount dword aligned */ /* set cpcount dword aligned */
if (cp_count & 3) if (cp_count & 3)
@ -1377,14 +1093,7 @@ static void gdth_copy_command(gdth_ha_str *ha)
ha->cmd_offs_dpmem += cp_count; ha->cmd_offs_dpmem += cp_count;
/* set offset and service, copy command to DPMEM */ /* set offset and service, copy command to DPMEM */
if (ha->type == GDT_ISA) { if (ha->type == GDT_PCI) {
dp2_ptr = ha->brd;
writew(dp_offset + DPMEM_COMMAND_OFFSET,
&dp2_ptr->u.ic.comm_queue[cmd_no].offset);
writew((u16)cmd_ptr->Service,
&dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
} else if (ha->type == GDT_PCI) {
dp6_ptr = ha->brd; dp6_ptr = ha->brd;
writew(dp_offset + DPMEM_COMMAND_OFFSET, writew(dp_offset + DPMEM_COMMAND_OFFSET,
&dp6_ptr->u.ic.comm_queue[cmd_no].offset); &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
@ -1430,13 +1139,7 @@ static void gdth_release_event(gdth_ha_str *ha)
if (ha->pccb->OpCode == GDT_INIT) if (ha->pccb->OpCode == GDT_INIT)
ha->pccb->Service |= 0x80; ha->pccb->Service |= 0x80;
if (ha->type == GDT_EISA) { if (ha->type == GDT_PCI) {
if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
outb(ha->pccb->Service, ha->bmic + LDOORREG);
} else if (ha->type == GDT_ISA) {
writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
} else if (ha->type == GDT_PCI) {
writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event); writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
} else if (ha->type == GDT_PCINEW) { } else if (ha->type == GDT_PCINEW) {
outb(1, PTR2USHORT(&ha->plx->ldoor_reg)); outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
@ -2433,9 +2136,6 @@ static int gdth_fill_cache_cmd(gdth_ha_str *ha, struct scsi_cmnd *scp,
TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n", TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
scp->cmnd[0],scp->cmd_len,hdrive)); scp->cmnd[0],scp->cmd_len,hdrive));
if (ha->type==GDT_EISA && ha->cmd_cnt>0)
return 0;
mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE; mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
/* test for READ_16, WRITE_16 if !mode64 ? --- /* test for READ_16, WRITE_16 if !mode64 ? ---
not required, should not occur due to error return on not required, should not occur due to error return on
@ -2613,9 +2313,6 @@ static int gdth_fill_raw_cmd(gdth_ha_str *ha, struct scsi_cmnd *scp, u8 b)
TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n", TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
scp->cmnd[0],b,t,l)); scp->cmnd[0],b,t,l));
if (ha->type==GDT_EISA && ha->cmd_cnt>0)
return 0;
mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE; mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
cmdp->Service = SCSIRAWSERVICE; cmdp->Service = SCSIRAWSERVICE;
@ -2778,9 +2475,6 @@ static int gdth_special_cmd(gdth_ha_str *ha, struct scsi_cmnd *scp)
cmdp= ha->pccb; cmdp= ha->pccb;
TRACE2(("gdth_special_cmd(): ")); TRACE2(("gdth_special_cmd(): "));
if (ha->type==GDT_EISA && ha->cmd_cnt>0)
return 0;
*cmdp = *cmndinfo->internal_cmd_str; *cmdp = *cmndinfo->internal_cmd_str;
cmdp->RequestBuffer = scp; cmdp->RequestBuffer = scp;
@ -2959,7 +2653,6 @@ static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
{ {
gdt6m_dpram_str __iomem *dp6m_ptr = NULL; gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
gdt6_dpram_str __iomem *dp6_ptr; gdt6_dpram_str __iomem *dp6_ptr;
gdt2_dpram_str __iomem *dp2_ptr;
struct scsi_cmnd *scp; struct scsi_cmnd *scp;
int rval, i; int rval, i;
u8 IStatus; u8 IStatus;
@ -3015,35 +2708,7 @@ static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
} }
#endif #endif
if (ha->type == GDT_EISA) { if (ha->type == GDT_PCI) {
if (IStatus & 0x80) { /* error flag */
IStatus &= ~0x80;
ha->status = inw(ha->bmic + MAILBOXREG+8);
TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
} else /* no error */
ha->status = S_OK;
ha->info = inl(ha->bmic + MAILBOXREG+12);
ha->service = inw(ha->bmic + MAILBOXREG+10);
ha->info2 = inl(ha->bmic + MAILBOXREG+4);
outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
} else if (ha->type == GDT_ISA) {
dp2_ptr = ha->brd;
if (IStatus & 0x80) { /* error flag */
IStatus &= ~0x80;
ha->status = readw(&dp2_ptr->u.ic.Status);
TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
} else /* no error */
ha->status = S_OK;
ha->info = readl(&dp2_ptr->u.ic.Info[0]);
ha->service = readw(&dp2_ptr->u.ic.Service);
ha->info2 = readl(&dp2_ptr->u.ic.Info[1]);
writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
} else if (ha->type == GDT_PCI) {
dp6_ptr = ha->brd; dp6_ptr = ha->brd;
if (IStatus & 0x80) { /* error flag */ if (IStatus & 0x80) { /* error flag */
IStatus &= ~0x80; IStatus &= ~0x80;
@ -3610,12 +3275,7 @@ static int gdth_async_event(gdth_ha_str *ha)
+ sizeof(u64); + sizeof(u64);
ha->cmd_cnt = 0; ha->cmd_cnt = 0;
gdth_copy_command(ha); gdth_copy_command(ha);
if (ha->type == GDT_EISA) printk("[PCI %d/%d] ",(u16)(ha->brd_phys>>8),
printk("[EISA slot %d] ",(u16)ha->brd_phys);
else if (ha->type == GDT_ISA)
printk("[DPMEM 0x%4X] ",(u16)ha->brd_phys);
else
printk("[PCI %d/%d] ",(u16)(ha->brd_phys>>8),
(u16)((ha->brd_phys>>3)&0x1f)); (u16)((ha->brd_phys>>3)&0x1f));
gdth_release_event(ha); gdth_release_event(ha);
} }
@ -3756,23 +3416,12 @@ static inline void gdth_timer_init(void)
static void __init internal_setup(char *str,int *ints) static void __init internal_setup(char *str,int *ints)
{ {
int i, argc; int i;
char *cur_str, *argv; char *cur_str, *argv;
TRACE2(("internal_setup() str %s ints[0] %d\n", TRACE2(("internal_setup() str %s ints[0] %d\n",
str ? str:"NULL", ints ? ints[0]:0)); str ? str:"NULL", ints ? ints[0]:0));
/* read irq[] from ints[] */
if (ints) {
argc = ints[0];
if (argc > 0) {
if (argc > MAXHA)
argc = MAXHA;
for (i = 0; i < argc; ++i)
irq[i] = ints[i+1];
}
}
/* analyse string */ /* analyse string */
argv = str; argv = str;
while (argv && (cur_str = strchr(argv, ':'))) { while (argv && (cur_str = strchr(argv, ':'))) {
@ -3799,8 +3448,6 @@ static void __init internal_setup(char *str,int *ints)
rescan = val; rescan = val;
else if (!strncmp(argv, "shared_access:", 14)) else if (!strncmp(argv, "shared_access:", 14))
shared_access = val; shared_access = val;
else if (!strncmp(argv, "probe_eisa_isa:", 15))
probe_eisa_isa = val;
else if (!strncmp(argv, "reserve_list:", 13)) { else if (!strncmp(argv, "reserve_list:", 13)) {
reserve_list[0] = val; reserve_list[0] = val;
for (i = 1; i < MAX_RES_ARGS; i++) { for (i = 1; i < MAX_RES_ARGS; i++) {
@ -3847,18 +3494,7 @@ static const char *gdth_ctr_name(gdth_ha_str *ha)
{ {
TRACE2(("gdth_ctr_name()\n")); TRACE2(("gdth_ctr_name()\n"));
if (ha->type == GDT_EISA) { if (ha->type == GDT_PCI) {
switch (ha->stype) {
case GDT3_ID:
return("GDT3000/3020");
case GDT3A_ID:
return("GDT3000A/3020A/3050A");
case GDT3B_ID:
return("GDT3000B/3010A");
}
} else if (ha->type == GDT_ISA) {
return("GDT2000/2020");
} else if (ha->type == GDT_PCI) {
switch (ha->pdev->device) { switch (ha->pdev->device) {
case PCI_DEVICE_ID_VORTEX_GDT60x0: case PCI_DEVICE_ID_VORTEX_GDT60x0:
return("GDT6000/6020/6050"); return("GDT6000/6020/6050");
@ -4528,22 +4164,17 @@ static int gdth_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
(NULL == (ha = gdth_find_ha(ctrt.ionode)))) (NULL == (ha = gdth_find_ha(ctrt.ionode))))
return -EFAULT; return -EFAULT;
if (ha->type == GDT_ISA || ha->type == GDT_EISA) { if (ha->type != GDT_PCIMPR) {
ctrt.type = (u8)((ha->stype>>20) - 0x10); ctrt.type = (u8)((ha->stype<<4) + 6);
} else { } else {
if (ha->type != GDT_PCIMPR) { ctrt.type = (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
ctrt.type = (u8)((ha->stype<<4) + 6); if (ha->stype >= 0x300)
} else { ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
ctrt.type = else
(ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe); ctrt.ext_type = 0x6000 | ha->stype;
if (ha->stype >= 0x300)
ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
else
ctrt.ext_type = 0x6000 | ha->stype;
}
ctrt.device_id = ha->pdev->device;
ctrt.sub_device_id = ha->pdev->subsystem_device;
} }
ctrt.device_id = ha->pdev->device;
ctrt.sub_device_id = ha->pdev->subsystem_device;
ctrt.info = ha->brd_phys; ctrt.info = ha->brd_phys;
ctrt.oem_id = ha->oem_id; ctrt.oem_id = ha->oem_id;
if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype))) if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
@ -4697,272 +4328,6 @@ static struct scsi_host_template gdth_template = {
.no_write_same = 1, .no_write_same = 1,
}; };
#ifdef CONFIG_ISA
static int __init gdth_isa_probe_one(u32 isa_bios)
{
struct Scsi_Host *shp;
gdth_ha_str *ha;
dma_addr_t scratch_dma_handle = 0;
int error, i;
if (!gdth_search_isa(isa_bios))
return -ENXIO;
shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
if (!shp)
return -ENOMEM;
ha = shost_priv(shp);
error = -ENODEV;
if (!gdth_init_isa(isa_bios,ha))
goto out_host_put;
/* controller found and initialized */
printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
isa_bios, ha->irq, ha->drq);
error = request_irq(ha->irq, gdth_interrupt, 0, "gdth", ha);
if (error) {
printk("GDT-ISA: Unable to allocate IRQ\n");
goto out_host_put;
}
error = request_dma(ha->drq, "gdth");
if (error) {
printk("GDT-ISA: Unable to allocate DMA channel\n");
goto out_free_irq;
}
set_dma_mode(ha->drq,DMA_MODE_CASCADE);
enable_dma(ha->drq);
shp->unchecked_isa_dma = 1;
shp->irq = ha->irq;
shp->dma_channel = ha->drq;
ha->hanum = gdth_ctr_count++;
ha->shost = shp;
ha->pccb = &ha->cmdext;
ha->ccb_phys = 0L;
ha->pdev = NULL;
error = -ENOMEM;
ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
&scratch_dma_handle);
if (!ha->pscratch)
goto out_dec_counters;
ha->scratch_phys = scratch_dma_handle;
ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
&scratch_dma_handle);
if (!ha->pmsg)
goto out_free_pscratch;
ha->msg_phys = scratch_dma_handle;
#ifdef INT_COAL
ha->coal_stat = pci_alloc_consistent(ha->pdev,
sizeof(gdth_coal_status) * MAXOFFSETS,
&scratch_dma_handle);
if (!ha->coal_stat)
goto out_free_pmsg;
ha->coal_stat_phys = scratch_dma_handle;
#endif
ha->scratch_busy = FALSE;
ha->req_first = NULL;
ha->tid_cnt = MAX_HDRIVES;
if (max_ids > 0 && max_ids < ha->tid_cnt)
ha->tid_cnt = max_ids;
for (i = 0; i < GDTH_MAXCMDS; ++i)
ha->cmd_tab[i].cmnd = UNUSED_CMND;
ha->scan_mode = rescan ? 0x10 : 0;
error = -ENODEV;
if (!gdth_search_drives(ha)) {
printk("GDT-ISA: Error during device scan\n");
goto out_free_coal_stat;
}
if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
hdr_channel = ha->bus_cnt;
ha->virt_bus = hdr_channel;
if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
shp->max_cmd_len = 16;
shp->max_id = ha->tid_cnt;
shp->max_lun = MAXLUN;
shp->max_channel = ha->bus_cnt;
spin_lock_init(&ha->smp_lock);
gdth_enable_int(ha);
error = scsi_add_host(shp, NULL);
if (error)
goto out_free_coal_stat;
list_add_tail(&ha->list, &gdth_instances);
gdth_timer_init();
scsi_scan_host(shp);
return 0;
out_free_coal_stat:
#ifdef INT_COAL
pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
ha->coal_stat, ha->coal_stat_phys);
out_free_pmsg:
#endif
pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
ha->pmsg, ha->msg_phys);
out_free_pscratch:
pci_free_consistent(ha->pdev, GDTH_SCRATCH,
ha->pscratch, ha->scratch_phys);
out_dec_counters:
gdth_ctr_count--;
out_free_irq:
free_irq(ha->irq, ha);
out_host_put:
scsi_host_put(shp);
return error;
}
#endif /* CONFIG_ISA */
#ifdef CONFIG_EISA
static int __init gdth_eisa_probe_one(u16 eisa_slot)
{
struct Scsi_Host *shp;
gdth_ha_str *ha;
dma_addr_t scratch_dma_handle = 0;
int error, i;
if (!gdth_search_eisa(eisa_slot))
return -ENXIO;
shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
if (!shp)
return -ENOMEM;
ha = shost_priv(shp);
error = -ENODEV;
if (!gdth_init_eisa(eisa_slot,ha))
goto out_host_put;
/* controller found and initialized */
printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
eisa_slot >> 12, ha->irq);
error = request_irq(ha->irq, gdth_interrupt, 0, "gdth", ha);
if (error) {
printk("GDT-EISA: Unable to allocate IRQ\n");
goto out_host_put;
}
shp->unchecked_isa_dma = 0;
shp->irq = ha->irq;
shp->dma_channel = 0xff;
ha->hanum = gdth_ctr_count++;
ha->shost = shp;
TRACE2(("EISA detect Bus 0: hanum %d\n", ha->hanum));
ha->pccb = &ha->cmdext;
ha->ccb_phys = 0L;
error = -ENOMEM;
ha->pdev = NULL;
ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
&scratch_dma_handle);
if (!ha->pscratch)
goto out_free_irq;
ha->scratch_phys = scratch_dma_handle;
ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
&scratch_dma_handle);
if (!ha->pmsg)
goto out_free_pscratch;
ha->msg_phys = scratch_dma_handle;
#ifdef INT_COAL
ha->coal_stat = pci_alloc_consistent(ha->pdev,
sizeof(gdth_coal_status) * MAXOFFSETS,
&scratch_dma_handle);
if (!ha->coal_stat)
goto out_free_pmsg;
ha->coal_stat_phys = scratch_dma_handle;
#endif
ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb,
sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL);
if (!ha->ccb_phys)
goto out_free_coal_stat;
ha->scratch_busy = FALSE;
ha->req_first = NULL;
ha->tid_cnt = MAX_HDRIVES;
if (max_ids > 0 && max_ids < ha->tid_cnt)
ha->tid_cnt = max_ids;
for (i = 0; i < GDTH_MAXCMDS; ++i)
ha->cmd_tab[i].cmnd = UNUSED_CMND;
ha->scan_mode = rescan ? 0x10 : 0;
if (!gdth_search_drives(ha)) {
printk("GDT-EISA: Error during device scan\n");
error = -ENODEV;
goto out_free_ccb_phys;
}
if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
hdr_channel = ha->bus_cnt;
ha->virt_bus = hdr_channel;
if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
shp->max_cmd_len = 16;
shp->max_id = ha->tid_cnt;
shp->max_lun = MAXLUN;
shp->max_channel = ha->bus_cnt;
spin_lock_init(&ha->smp_lock);
gdth_enable_int(ha);
error = scsi_add_host(shp, NULL);
if (error)
goto out_free_ccb_phys;
list_add_tail(&ha->list, &gdth_instances);
gdth_timer_init();
scsi_scan_host(shp);
return 0;
out_free_ccb_phys:
pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str),
PCI_DMA_BIDIRECTIONAL);
out_free_coal_stat:
#ifdef INT_COAL
pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
ha->coal_stat, ha->coal_stat_phys);
out_free_pmsg:
#endif
pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
ha->pmsg, ha->msg_phys);
out_free_pscratch:
pci_free_consistent(ha->pdev, GDTH_SCRATCH,
ha->pscratch, ha->scratch_phys);
out_free_irq:
free_irq(ha->irq, ha);
gdth_ctr_count--;
out_host_put:
scsi_host_put(shp);
return error;
}
#endif /* CONFIG_EISA */
#ifdef CONFIG_PCI
static int gdth_pci_probe_one(gdth_pci_str *pcistr, gdth_ha_str **ha_out) static int gdth_pci_probe_one(gdth_pci_str *pcistr, gdth_ha_str **ha_out)
{ {
struct Scsi_Host *shp; struct Scsi_Host *shp;
@ -5105,7 +4470,6 @@ static int gdth_pci_probe_one(gdth_pci_str *pcistr, gdth_ha_str **ha_out)
scsi_host_put(shp); scsi_host_put(shp);
return error; return error;
} }
#endif /* CONFIG_PCI */
static void gdth_remove_one(gdth_ha_str *ha) static void gdth_remove_one(gdth_ha_str *ha)
{ {
@ -5125,10 +4489,6 @@ static void gdth_remove_one(gdth_ha_str *ha)
if (shp->irq) if (shp->irq)
free_irq(shp->irq,ha); free_irq(shp->irq,ha);
#ifdef CONFIG_ISA
if (shp->dma_channel != 0xff)
free_dma(shp->dma_channel);
#endif
#ifdef INT_COAL #ifdef INT_COAL
if (ha->coal_stat) if (ha->coal_stat)
pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
@ -5181,26 +4541,6 @@ static int __init gdth_init(void)
gdth_clear_events(); gdth_clear_events();
timer_setup(&gdth_timer, gdth_timeout, 0); timer_setup(&gdth_timer, gdth_timeout, 0);
/* As default we do not probe for EISA or ISA controllers */
if (probe_eisa_isa) {
/* scanning for controllers, at first: ISA controller */
#ifdef CONFIG_ISA
u32 isa_bios;
for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
isa_bios += 0x8000UL)
gdth_isa_probe_one(isa_bios);
#endif
#ifdef CONFIG_EISA
{
u16 eisa_slot;
for (eisa_slot = 0x1000; eisa_slot <= 0x8000;
eisa_slot += 0x1000)
gdth_eisa_probe_one(eisa_slot);
}
#endif
}
#ifdef CONFIG_PCI
/* scanning for PCI controllers */ /* scanning for PCI controllers */
if (pci_register_driver(&gdth_pci_driver)) { if (pci_register_driver(&gdth_pci_driver)) {
gdth_ha_str *ha; gdth_ha_str *ha;
@ -5209,7 +4549,6 @@ static int __init gdth_init(void)
gdth_remove_one(ha); gdth_remove_one(ha);
return -ENODEV; return -ENODEV;
} }
#endif /* CONFIG_PCI */
TRACE2(("gdth_detect() %d controller detected\n", gdth_ctr_count)); TRACE2(("gdth_detect() %d controller detected\n", gdth_ctr_count));
@ -5230,9 +4569,7 @@ static void __exit gdth_exit(void)
del_timer_sync(&gdth_timer); del_timer_sync(&gdth_timer);
#endif #endif
#ifdef CONFIG_PCI
pci_unregister_driver(&gdth_pci_driver); pci_unregister_driver(&gdth_pci_driver);
#endif
list_for_each_entry(ha, &gdth_instances, list) list_for_each_entry(ha, &gdth_instances, list)
gdth_remove_one(ha); gdth_remove_one(ha);

30
drivers/scsi/gdth.h
View File

@ -38,17 +38,9 @@
#define OEM_ID_INTEL 0x8000 #define OEM_ID_INTEL 0x8000
/* controller classes */ /* controller classes */
#define GDT_ISA 0x01 /* ISA controller */
#define GDT_EISA 0x02 /* EISA controller */
#define GDT_PCI 0x03 /* PCI controller */ #define GDT_PCI 0x03 /* PCI controller */
#define GDT_PCINEW 0x04 /* new PCI controller */ #define GDT_PCINEW 0x04 /* new PCI controller */
#define GDT_PCIMPR 0x05 /* PCI MPR controller */ #define GDT_PCIMPR 0x05 /* PCI MPR controller */
/* GDT_EISA, controller subtypes EISA */
#define GDT3_ID 0x0130941c /* GDT3000/3020 */
#define GDT3A_ID 0x0230941c /* GDT3000A/3020A/3050A */
#define GDT3B_ID 0x0330941c /* GDT3000B/3010A */
/* GDT_ISA */
#define GDT2_ID 0x0120941c /* GDT2000/2020 */
#ifndef PCI_DEVICE_ID_VORTEX_GDT60x0 #ifndef PCI_DEVICE_ID_VORTEX_GDT60x0
/* GDT_PCI */ /* GDT_PCI */
@ -281,17 +273,6 @@
#define GDTH_DATA_IN 0x01000000L /* data from target */ #define GDTH_DATA_IN 0x01000000L /* data from target */
#define GDTH_DATA_OUT 0x00000000L /* data to target */ #define GDTH_DATA_OUT 0x00000000L /* data to target */
/* BMIC registers (EISA controllers) */
#define ID0REG 0x0c80 /* board ID */
#define EINTENABREG 0x0c89 /* interrupt enable */
#define SEMA0REG 0x0c8a /* command semaphore */
#define SEMA1REG 0x0c8b /* status semaphore */
#define LDOORREG 0x0c8d /* local doorbell */
#define EDENABREG 0x0c8e /* EISA system doorbell enab. */
#define EDOORREG 0x0c8f /* EISA system doorbell */
#define MAILBOXREG 0x0c90 /* mailbox reg. (16 bytes) */
#define EISAREG 0x0cc0 /* EISA configuration */
/* other defines */ /* other defines */
#define LINUX_OS 8 /* used for cache optim. */ #define LINUX_OS 8 /* used for cache optim. */
#define SECS32 0x1f /* round capacity */ #define SECS32 0x1f /* round capacity */
@ -706,21 +687,11 @@ typedef struct {
u8 fw_magic; /* contr. ID from firmware */ u8 fw_magic; /* contr. ID from firmware */
} __attribute__((packed)) gdt_pci_sram; } __attribute__((packed)) gdt_pci_sram;
/* SRAM structure EISA controllers (but NOT GDT3000/3020) */
typedef struct {
u8 os_used[16]; /* OS code per service */
u16 need_deinit; /* switch betw. BIOS/driver */
u8 switch_support; /* see need_deinit */
u8 padding;
} __attribute__((packed)) gdt_eisa_sram;
/* DPRAM ISA controllers */ /* DPRAM ISA controllers */
typedef struct { typedef struct {
union { union {
struct { struct {
u8 bios_used[0x3c00-32]; /* 15KB - 32Bytes BIOS */ u8 bios_used[0x3c00-32]; /* 15KB - 32Bytes BIOS */
u32 magic; /* controller (EISA) ID */
u16 need_deinit; /* switch betw. BIOS/driver */ u16 need_deinit; /* switch betw. BIOS/driver */
u8 switch_support; /* see need_deinit */ u8 switch_support; /* see need_deinit */
u8 padding[9]; u8 padding[9];
@ -843,7 +814,6 @@ typedef struct {
u16 cache_feat; /* feat. cache serv. (s/g,..)*/ u16 cache_feat; /* feat. cache serv. (s/g,..)*/
u16 raw_feat; /* feat. raw service (s/g,..)*/ u16 raw_feat; /* feat. raw service (s/g,..)*/
u16 screen_feat; /* feat. raw service (s/g,..)*/ u16 screen_feat; /* feat. raw service (s/g,..)*/
u16 bmic; /* BMIC address (EISA) */
void __iomem *brd; /* DPRAM address */ void __iomem *brd; /* DPRAM address */
u32 brd_phys; /* slot number/BIOS address */ u32 brd_phys; /* slot number/BIOS address */
gdt6c_plx_regs *plx; /* PLX regs (new PCI contr.) */ gdt6c_plx_regs *plx; /* PLX regs (new PCI contr.) */