drm/amdgpu/sriov:move in_reset to adev and rename
currently in_reset is only used in sriov gpu reset, and it will be used for other non-gfx hw component later, like PSP, so move it from gfx to adev and rename to in_sriov_reset make more sense. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1018,7 +1018,6 @@ struct amdgpu_gfx {
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/* reset mask */
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uint32_t grbm_soft_reset;
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uint32_t srbm_soft_reset;
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bool in_reset;
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/* s3/s4 mask */
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bool in_suspend;
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/* NGG */
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@ -1583,6 +1582,7 @@ struct amdgpu_device {
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/* record last mm index being written through WREG32*/
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unsigned long last_mm_index;
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bool in_sriov_reset;
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};
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static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
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@ -2690,7 +2690,7 @@ int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job)
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mutex_lock(&adev->virt.lock_reset);
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atomic_inc(&adev->gpu_reset_counter);
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adev->gfx.in_reset = true;
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adev->in_sriov_reset = true;
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/* block TTM */
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resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
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@ -2801,7 +2801,7 @@ int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job)
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dev_info(adev->dev, "GPU reset successed!\n");
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}
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adev->gfx.in_reset = false;
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adev->in_sriov_reset = false;
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mutex_unlock(&adev->virt.lock_reset);
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return r;
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}
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@ -4811,7 +4811,7 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring)
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gfx_v8_0_kiq_setting(ring);
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if (adev->gfx.in_reset) { /* for GPU_RESET case */
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if (adev->in_sriov_reset) { /* for GPU_RESET case */
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/* reset MQD to a clean status */
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if (adev->gfx.mec.mqd_backup[mqd_idx])
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memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));
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@ -4848,7 +4848,7 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)
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struct vi_mqd *mqd = ring->mqd_ptr;
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int mqd_idx = ring - &adev->gfx.compute_ring[0];
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if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
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if (!adev->in_sriov_reset && !adev->gfx.in_suspend) {
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memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
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((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
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((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
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@ -4860,7 +4860,7 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)
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if (adev->gfx.mec.mqd_backup[mqd_idx])
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memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation));
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} else if (adev->gfx.in_reset) { /* for GPU_RESET case */
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} else if (adev->in_sriov_reset) { /* for GPU_RESET case */
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/* reset MQD to a clean status */
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if (adev->gfx.mec.mqd_backup[mqd_idx])
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memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));
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@ -2698,7 +2698,7 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
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gfx_v9_0_kiq_setting(ring);
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if (adev->gfx.in_reset) { /* for GPU_RESET case */
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if (adev->in_sriov_reset) { /* for GPU_RESET case */
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/* reset MQD to a clean status */
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if (adev->gfx.mec.mqd_backup[mqd_idx])
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memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
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@ -2736,7 +2736,7 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
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struct v9_mqd *mqd = ring->mqd_ptr;
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int mqd_idx = ring - &adev->gfx.compute_ring[0];
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if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
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if (!adev->in_sriov_reset && !adev->gfx.in_suspend) {
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memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
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((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
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((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
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@ -2748,7 +2748,7 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
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if (adev->gfx.mec.mqd_backup[mqd_idx])
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memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
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} else if (adev->gfx.in_reset) { /* for GPU_RESET case */
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} else if (adev->in_sriov_reset) { /* for GPU_RESET case */
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/* reset MQD to a clean status */
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if (adev->gfx.mec.mqd_backup[mqd_idx])
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memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
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