ARM: vexpress: migrate DCSCB to the new MCPM backend abstraction
Signed-off-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Nicolas Pitre
Olof Johansson
parent
03fd5db717
commit
323ab95339
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@ -12,7 +12,6 @@
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <linux/errno.h>
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#include <linux/of_address.h>
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#include <linux/vexpress.h>
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@ -36,163 +35,102 @@
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#define KFC_CFG_W 0x2c
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#define DCS_CFG_R 0x30
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/*
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* We can't use regular spinlocks. In the switcher case, it is possible
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* for an outbound CPU to call power_down() while its inbound counterpart
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* is already live using the same logical CPU number which trips lockdep
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* debugging.
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*/
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static arch_spinlock_t dcscb_lock = __ARCH_SPIN_LOCK_UNLOCKED;
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static void __iomem *dcscb_base;
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static int dcscb_use_count[4][2];
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static int dcscb_allcpus_mask[2];
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static int dcscb_power_up(unsigned int cpu, unsigned int cluster)
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static int dcscb_cpu_powerup(unsigned int cpu, unsigned int cluster)
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{
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unsigned int rst_hold, cpumask = (1 << cpu);
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unsigned int all_mask;
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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if (cluster >= 2 || !(cpumask & dcscb_allcpus_mask[cluster]))
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return -EINVAL;
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all_mask = dcscb_allcpus_mask[cluster];
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/*
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* Since this is called with IRQs enabled, and no arch_spin_lock_irq
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* variant exists, we need to disable IRQs manually here.
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*/
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local_irq_disable();
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arch_spin_lock(&dcscb_lock);
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dcscb_use_count[cpu][cluster]++;
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if (dcscb_use_count[cpu][cluster] == 1) {
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rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
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if (rst_hold & (1 << 8)) {
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/* remove cluster reset and add individual CPU's reset */
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rst_hold &= ~(1 << 8);
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rst_hold |= all_mask;
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}
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rst_hold &= ~(cpumask | (cpumask << 4));
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writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
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} else if (dcscb_use_count[cpu][cluster] != 2) {
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/*
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* The only possible values are:
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* 0 = CPU down
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* 1 = CPU (still) up
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* 2 = CPU requested to be up before it had a chance
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* to actually make itself down.
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* Any other value is a bug.
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*/
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BUG();
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}
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arch_spin_unlock(&dcscb_lock);
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local_irq_enable();
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rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
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rst_hold &= ~(cpumask | (cpumask << 4));
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writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
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return 0;
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}
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static void dcscb_power_down(void)
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static int dcscb_cluster_powerup(unsigned int cluster)
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{
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unsigned int mpidr, cpu, cluster, rst_hold, cpumask, all_mask;
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bool last_man = false, skip_wfi = false;
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unsigned int rst_hold;
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mpidr = read_cpuid_mpidr();
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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cpumask = (1 << cpu);
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pr_debug("%s: cluster %u\n", __func__, cluster);
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if (cluster >= 2)
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return -EINVAL;
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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BUG_ON(cluster >= 2 || !(cpumask & dcscb_allcpus_mask[cluster]));
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all_mask = dcscb_allcpus_mask[cluster];
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__mcpm_cpu_going_down(cpu, cluster);
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arch_spin_lock(&dcscb_lock);
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BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
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dcscb_use_count[cpu][cluster]--;
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if (dcscb_use_count[cpu][cluster] == 0) {
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rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
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rst_hold |= cpumask;
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if (((rst_hold | (rst_hold >> 4)) & all_mask) == all_mask) {
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rst_hold |= (1 << 8);
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last_man = true;
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}
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writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
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} else if (dcscb_use_count[cpu][cluster] == 1) {
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/*
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* A power_up request went ahead of us.
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* Even if we do not want to shut this CPU down,
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* the caller expects a certain state as if the WFI
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* was aborted. So let's continue with cache cleaning.
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*/
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skip_wfi = true;
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} else
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BUG();
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if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
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arch_spin_unlock(&dcscb_lock);
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/* Flush all cache levels for this cluster. */
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v7_exit_coherency_flush(all);
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/*
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* A full outer cache flush could be needed at this point
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* on platforms with such a cache, depending on where the
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* outer cache sits. In some cases the notion of a "last
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* cluster standing" would need to be implemented if the
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* outer cache is shared across clusters. In any case, when
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* the outer cache needs flushing, there is no concurrent
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* access to the cache controller to worry about and no
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* special locking besides what is already provided by the
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* MCPM state machinery is needed.
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*/
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/*
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* Disable cluster-level coherency by masking
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* incoming snoops and DVM messages:
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*/
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cci_disable_port_by_cpu(mpidr);
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__mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
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} else {
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arch_spin_unlock(&dcscb_lock);
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/* Disable and flush the local CPU cache. */
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v7_exit_coherency_flush(louis);
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}
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__mcpm_cpu_down(cpu, cluster);
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/* Now we are prepared for power-down, do it: */
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dsb();
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if (!skip_wfi)
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wfi();
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/* Not dead at this point? Let our caller cope. */
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/* remove cluster reset and add individual CPU's reset */
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rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
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rst_hold &= ~(1 << 8);
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rst_hold |= dcscb_allcpus_mask[cluster];
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writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
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return 0;
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}
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static const struct mcpm_platform_ops dcscb_power_ops = {
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.power_up = dcscb_power_up,
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.power_down = dcscb_power_down,
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};
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static void __init dcscb_usage_count_init(void)
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static void dcscb_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster)
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{
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unsigned int mpidr, cpu, cluster;
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mpidr = read_cpuid_mpidr();
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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unsigned int rst_hold;
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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BUG_ON(cluster >= 2 || !((1 << cpu) & dcscb_allcpus_mask[cluster]));
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dcscb_use_count[cpu][cluster] = 1;
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rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
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rst_hold |= (1 << cpu);
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writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
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}
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static void dcscb_cluster_powerdown_prepare(unsigned int cluster)
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{
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unsigned int rst_hold;
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pr_debug("%s: cluster %u\n", __func__, cluster);
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BUG_ON(cluster >= 2);
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rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
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rst_hold |= (1 << 8);
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writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
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}
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static void dcscb_cpu_cache_disable(void)
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{
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/* Disable and flush the local CPU cache. */
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v7_exit_coherency_flush(louis);
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}
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static void dcscb_cluster_cache_disable(void)
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{
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/* Flush all cache levels for this cluster. */
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v7_exit_coherency_flush(all);
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/*
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* A full outer cache flush could be needed at this point
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* on platforms with such a cache, depending on where the
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* outer cache sits. In some cases the notion of a "last
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* cluster standing" would need to be implemented if the
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* outer cache is shared across clusters. In any case, when
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* the outer cache needs flushing, there is no concurrent
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* access to the cache controller to worry about and no
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* special locking besides what is already provided by the
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* MCPM state machinery is needed.
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*/
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/*
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* Disable cluster-level coherency by masking
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* incoming snoops and DVM messages:
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*/
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cci_disable_port_by_cpu(read_cpuid_mpidr());
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}
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static const struct mcpm_platform_ops dcscb_power_ops = {
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.cpu_powerup = dcscb_cpu_powerup,
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.cluster_powerup = dcscb_cluster_powerup,
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.cpu_powerdown_prepare = dcscb_cpu_powerdown_prepare,
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.cluster_powerdown_prepare = dcscb_cluster_powerdown_prepare,
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.cpu_cache_disable = dcscb_cpu_cache_disable,
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.cluster_cache_disable = dcscb_cluster_cache_disable,
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};
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extern void dcscb_power_up_setup(unsigned int affinity_level);
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static int __init dcscb_init(void)
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@ -213,7 +151,6 @@ static int __init dcscb_init(void)
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cfg = readl_relaxed(dcscb_base + DCS_CFG_R);
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dcscb_allcpus_mask[0] = (1 << (((cfg >> 16) >> (0 << 2)) & 0xf)) - 1;
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dcscb_allcpus_mask[1] = (1 << (((cfg >> 16) >> (1 << 2)) & 0xf)) - 1;
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dcscb_usage_count_init();
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ret = mcpm_platform_register(&dcscb_power_ops);
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if (!ret)
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