coresight: Adding coresight support for arm64 architecture
Most CoreSight blocks are 64-bit ready. As such move configuration entries from "arch/arm/Kconfig.config" to the driver's subdirectory and source the newly created Kconfig from architecture specific Kconfig.debug files. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Mathieu Poirier
Greg Kroah-Hartman
parent
72f641fe68
commit
3288731e62
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@ -1610,59 +1610,6 @@ config DEBUG_SET_MODULE_RONX
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against certain classes of kernel exploits.
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If in doubt, say "N".
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menuconfig CORESIGHT
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bool "CoreSight Tracing Support"
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select ARM_AMBA
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help
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This framework provides a kernel interface for the CoreSight debug
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and trace drivers to register themselves with. It's intended to build
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a topological view of the CoreSight components based on a DT
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specification and configure the right serie of components when a
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trace source gets enabled.
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source "drivers/coresight/Kconfig"
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if CORESIGHT
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config CORESIGHT_LINKS_AND_SINKS
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bool "CoreSight Link and Sink drivers"
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help
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This enables support for CoreSight link and sink drivers that are
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responsible for transporting and collecting the trace data
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respectively. Link and sinks are dynamically aggregated with a trace
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entity at run time to form a complete trace path.
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config CORESIGHT_LINK_AND_SINK_TMC
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bool "Coresight generic TMC driver"
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depends on CORESIGHT_LINKS_AND_SINKS
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help
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This enables support for the Trace Memory Controller driver. Depending
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on its configuration the device can act as a link (embedded trace router
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- ETR) or sink (embedded trace FIFO). The driver complies with the
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generic implementation of the component without special enhancement or
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added features.
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config CORESIGHT_SINK_TPIU
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bool "Coresight generic TPIU driver"
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depends on CORESIGHT_LINKS_AND_SINKS
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help
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This enables support for the Trace Port Interface Unit driver, responsible
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for bridging the gap between the on-chip coresight components and a trace
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port collection engine, typically connected to an external host for use
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case capturing more traces than the on-board coresight memory can handle.
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config CORESIGHT_SINK_ETBV10
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bool "Coresight ETBv1.0 driver"
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depends on CORESIGHT_LINKS_AND_SINKS
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help
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This enables support for the Embedded Trace Buffer version 1.0 driver
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that complies with the generic implementation of the component without
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special enhancement or added features.
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config CORESIGHT_SOURCE_ETM3X
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bool "CoreSight Embedded Trace Macrocell 3.x driver"
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select CORESIGHT_LINKS_AND_SINKS
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help
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This driver provides support for processor ETM3.x and PTM1.x modules,
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which allows tracing the instructions that a processor is executing
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This is primarily useful for instruction level tracing. Depending
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the ETM version data tracing may also be available.
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endif
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endmenu
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@ -89,4 +89,6 @@ config DEBUG_ALIGN_RODATA
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If in doubt, say N
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source "drivers/coresight/Kconfig"
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endmenu
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@ -0,0 +1,61 @@
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#
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# Coresight configuration
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#
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menuconfig CORESIGHT
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bool "CoreSight Tracing Support"
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select ARM_AMBA
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help
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This framework provides a kernel interface for the CoreSight debug
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and trace drivers to register themselves with. It's intended to build
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a topological view of the CoreSight components based on a DT
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specification and configure the right serie of components when a
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trace source gets enabled.
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if CORESIGHT
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config CORESIGHT_LINKS_AND_SINKS
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bool "CoreSight Link and Sink drivers"
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help
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This enables support for CoreSight link and sink drivers that are
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responsible for transporting and collecting the trace data
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respectively. Link and sinks are dynamically aggregated with a trace
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entity at run time to form a complete trace path.
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config CORESIGHT_LINK_AND_SINK_TMC
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bool "Coresight generic TMC driver"
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depends on CORESIGHT_LINKS_AND_SINKS
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help
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This enables support for the Trace Memory Controller driver.
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Depending on its configuration the device can act as a link (embedded
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trace router - ETR) or sink (embedded trace FIFO). The driver
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complies with the generic implementation of the component without
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special enhancement or added features.
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config CORESIGHT_SINK_TPIU
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bool "Coresight generic TPIU driver"
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depends on CORESIGHT_LINKS_AND_SINKS
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help
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This enables support for the Trace Port Interface Unit driver,
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responsible for bridging the gap between the on-chip coresight
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components and a trace for bridging the gap between the on-chip
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coresight components and a trace port collection engine, typically
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connected to an external host for use case capturing more traces than
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the on-board coresight memory can handle.
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config CORESIGHT_SINK_ETBV10
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bool "Coresight ETBv1.0 driver"
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depends on CORESIGHT_LINKS_AND_SINKS
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help
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This enables support for the Embedded Trace Buffer version 1.0 driver
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that complies with the generic implementation of the component without
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special enhancement or added features.
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config CORESIGHT_SOURCE_ETM3X
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bool "CoreSight Embedded Trace Macrocell 3.x driver"
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depends on !ARM64
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select CORESIGHT_LINKS_AND_SINKS
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help
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This driver provides support for processor ETM3.x and PTM1.x modules,
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which allows tracing the instructions that a processor is executing
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This is primarily useful for instruction level tracing. Depending
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the ETM version data tracing may also be available.
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endif
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