p71924506
/
linux_old1
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

thermal: exynos: Add support for TRIM_RELOAD feature at Exynos3250 

This patch add support for TRIM_RELOAD feature at Exynos3250. The TMu of
Exynos3250 has two TRIMINFO_CON register and must need to set RELOAD bit
before reading TRIMINFO register.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: Eduardo Valentin <edubezval@gmail.com>
Cc: Amit Daniel Kachhap <amit.daniel@samsung.com>
Reviewed-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
This commit is contained in:
Chanwoo Choi 2014-09-03 12:09:03 +09:00 committed by Eduardo Valentin
parent 56c64da7aa
commit 32a7416423
2 changed files with 12 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/thermal/samsung/exynos_tmu_data.c
View File

@ -87,6 +87,9 @@ struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
#if defined(CONFIG_SOC_EXYNOS3250) #if defined(CONFIG_SOC_EXYNOS3250)
static const struct exynos_tmu_registers exynos3250_tmu_registers = { static const struct exynos_tmu_registers exynos3250_tmu_registers = {
.triminfo_data = EXYNOS_TMU_REG_TRIMINFO, .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
.triminfo_ctrl[0] = EXYNOS_TMU_TRIMINFO_CON1,
.triminfo_ctrl[1] = EXYNOS_TMU_TRIMINFO_CON2,
.triminfo_ctrl_count = 2,
.tmu_ctrl = EXYNOS_TMU_REG_CONTROL, .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
.test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT, .test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT, .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
@ -147,8 +150,10 @@ static const struct exynos_tmu_registers exynos3250_tmu_registers = {
.temp_level = 95, \ .temp_level = 95, \
}, \ }, \
.freq_tab_count = 2, \ .freq_tab_count = 2, \
.triminfo_reload[0] = EXYNOS_TRIMINFO_RELOAD_ENABLE, \
.triminfo_reload[1] = EXYNOS_TRIMINFO_RELOAD_ENABLE, \
.registers = &exynos3250_tmu_registers, \ .registers = &exynos3250_tmu_registers, \
.features = (TMU_SUPPORT_EMULATION | \ .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \ TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
TMU_SUPPORT_EMUL_TIME) TMU_SUPPORT_EMUL_TIME)
#endif #endif
@ -169,7 +174,7 @@ struct exynos_tmu_init_data const exynos3250_default_tmu_data = {
#if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250) #if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
static const struct exynos_tmu_registers exynos4412_tmu_registers = { static const struct exynos_tmu_registers exynos4412_tmu_registers = {
.triminfo_data = EXYNOS_TMU_REG_TRIMINFO, .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
.triminfo_ctrl[0] = EXYNOS_TMU_TRIMINFO_CON, .triminfo_ctrl[0] = EXYNOS_TMU_TRIMINFO_CON2,
.triminfo_ctrl_count = 1, .triminfo_ctrl_count = 1,
.tmu_ctrl = EXYNOS_TMU_REG_CONTROL, .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
.test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT, .test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,

7
drivers/thermal/samsung/exynos_tmu_data.h
View File

@ -39,14 +39,17 @@
#define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8 #define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8
#define EXYNOS_TMU_CORE_EN_SHIFT 0 #define EXYNOS_TMU_CORE_EN_SHIFT 0
/* Exynos3250 specific registers */
#define EXYNOS_TMU_TRIMINFO_CON1 0x10
/* Exynos4210 specific registers */ /* Exynos4210 specific registers */
#define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44 #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44
#define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50 #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50
#define EXYNOS4210_TMU_TRIG_LEVEL_MASK 0x1111 #define EXYNOS4210_TMU_TRIG_LEVEL_MASK 0x1111
/* Exynos5250 and Exynos4412 specific registers */ /* Exynos5250, Exynos4412, Exynos3250 specific registers */
#define EXYNOS_TMU_TRIMINFO_CON 0x14 #define EXYNOS_TMU_TRIMINFO_CON2 0x14
#define EXYNOS_THD_TEMP_RISE 0x50 #define EXYNOS_THD_TEMP_RISE 0x50
#define EXYNOS_THD_TEMP_FALL 0x54 #define EXYNOS_THD_TEMP_FALL 0x54
#define EXYNOS_EMUL_CON 0x80 #define EXYNOS_EMUL_CON 0x80