This pull request contains Broadcom ARM/ARM64/MIPS SoCs changes for 4.15
(second part), please pull the following: - Markus updates the Broadcom STB DPFE driver to avoid loading the firmware when unnecessary to accomodate for specific platform restrictions - Florian adds support for the Broadcom Hurricane 2 SoC iProc PLL clock needed to get the proper CPU clock frequency -----BEGIN PGP SIGNATURE----- iQIcBAABCAAGBQJZ6o4yAAoJEIfQlpxEBwcEs3MQAJ9bBFsnLu3hNFM7WNuXgVDS z4/BYsVUhPzwz2lLB/OMsKU8xkGd/d7DcPvziMpvgWzTXoVEboXWtN5S2ReiVYja Pyl0UMTmT6Jo1z+8WQkWJROUYmaLQzVHr/J3q15FItNS6gvsxntiDYUVLHtIe+g2 3IOTDSVSptPoYYxWi3PiBsXfjb+ja/ob01K8cQh+3AcjopRTE9F7l9EXhUJWOJ9Y 21eCyCiPVdjFKfV2etby4XcTqV1LrvJEhmpaRBsn+jitvWYdaMb4+jwUv58nf7SF JaSBAjSRZ29FoVpUryHk9/yBt5NBv2WyAyizMG95JXeOnd2QDTi5RltxiG20kvBf Q9pm8w0FvAM+RmKE/eFHXil7jJOczuSoen+vOXbvvxaBP6vSVGkrGt/aEMvUCr2a Z+/fogKTIehQZhfrrkw1t5vLcmTGPYidggFPxED22juPpy9weVKqMiU02n6F7LpC NsyCtmooXVB+KBcMX71G7ywO9y5bz3Tqmn6nYrjf6Lyz7WoDPn1FlDxlvNfUi4uy 6rhmvwG1b4BT5ksZzu99I9uNhlVNQ1QxHetkpeHgQ/GWYGzCSYqewIdrooEhItyZ zibeLlUPJVIu338MYPjoUa2VSGwD2uy1b//wQW+qnA+fSDWw/v7vLW3/svo7D6Ov C8dNRSRXXyeZmpfejFPW =ecY1 -----END PGP SIGNATURE----- Merge tag 'arm-soc/for-4.15/drivers-part2' of http://github.com/Broadcom/stblinux into next/drivers Pull "Broadcom drivers changes for 4.15 (part 2)" from Florian Fainelli: This pull request contains Broadcom ARM/ARM64/MIPS SoCs changes for 4.15 (second part), please pull the following: - Markus updates the Broadcom STB DPFE driver to avoid loading the firmware when unnecessary to accomodate for specific platform restrictions - Florian adds support for the Broadcom Hurricane 2 SoC iProc PLL clock needed to get the proper CPU clock frequency * tag 'arm-soc/for-4.15/drivers-part2' of http://github.com/Broadcom/stblinux: clk: bcm: Add Broadcom Hurricane 2 clock support memory: brcmstb: dpfe: skip downloading firmware when possible memory: brcmstb: dpfe: introduce is_dcpu_enabled()
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commit
3330becb47
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@ -30,6 +30,15 @@ config CLK_BCM_CYGNUS
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help
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Enable common clock framework support for the Broadcom Cygnus SoC
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config CLK_BCM_HR2
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bool "Broadcom Hurricane 2 clock support"
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depends on ARCH_BCM_HR2 || COMPILE_TEST
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select COMMON_CLK_IPROC
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default ARCH_BCM_HR2
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help
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Enable common clock framework support for the Broadcom Hurricane 2
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SoC
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config CLK_BCM_NSP
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bool "Broadcom Northstar/Northstar Plus clock support"
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depends on ARCH_BCM_5301X || ARCH_BCM_NSP || COMPILE_TEST
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@ -8,6 +8,7 @@ obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
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obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835-aux.o
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obj-$(CONFIG_ARCH_BCM_53573) += clk-bcm53573-ilp.o
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obj-$(CONFIG_CLK_BCM_CYGNUS) += clk-cygnus.o
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obj-$(CONFIG_CLK_BCM_HR2) += clk-hr2.o
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obj-$(CONFIG_CLK_BCM_NSP) += clk-nsp.o
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obj-$(CONFIG_CLK_BCM_NS2) += clk-ns2.o
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obj-$(CONFIG_CLK_BCM_SR) += clk-sr.o
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@ -0,0 +1,27 @@
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/*
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* Copyright (C) 2017 Broadcom
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "clk-iproc.h"
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static void __init hr2_armpll_init(struct device_node *node)
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{
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iproc_armpll_setup(node);
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}
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CLK_OF_DECLARE(hr2_armpll, "brcm,hr2-armpll", hr2_armpll_init);
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@ -202,17 +202,26 @@ static const u32 dpfe_commands[DPFE_CMD_MAX][MSG_FIELD_MAX] = {
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},
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};
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static bool is_dcpu_enabled(void __iomem *regs)
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{
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u32 val;
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val = readl_relaxed(regs + REG_DCPU_RESET);
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return !(val & DCPU_RESET_MASK);
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}
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static void __disable_dcpu(void __iomem *regs)
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{
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u32 val;
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/* Check if DCPU is running */
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if (!is_dcpu_enabled(regs))
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return;
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/* Put DCPU in reset if it's running. */
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val = readl_relaxed(regs + REG_DCPU_RESET);
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if (!(val & DCPU_RESET_MASK)) {
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/* Put DCPU in reset */
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val |= (1 << DCPU_RESET_SHIFT);
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writel_relaxed(val, regs + REG_DCPU_RESET);
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}
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val |= (1 << DCPU_RESET_SHIFT);
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writel_relaxed(val, regs + REG_DCPU_RESET);
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}
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static void __enable_dcpu(void __iomem *regs)
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@ -422,13 +431,25 @@ static int brcmstb_dpfe_download_firmware(struct platform_device *pdev,
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const void *fw_blob;
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int ret;
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priv = platform_get_drvdata(pdev);
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/*
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* Skip downloading the firmware if the DCPU is already running and
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* responding to commands.
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*/
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if (is_dcpu_enabled(priv->regs)) {
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u32 response[MSG_FIELD_MAX];
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ret = __send_command(priv, DPFE_CMD_GET_INFO, response);
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if (!ret)
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return 0;
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}
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ret = request_firmware(&fw, FIRMWARE_NAME, dev);
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/* request_firmware() prints its own error messages. */
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if (ret)
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return ret;
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priv = platform_get_drvdata(pdev);
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ret = __verify_firmware(init, fw);
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if (ret)
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return -EFAULT;
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