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drm/amd/display: change generic_reg_wait to void. 

we were only checking the return value in one place, thus changing
generic_reg_wait from int to void and reading the register instead of
getting it from generic_reg_wait, when we need the return value.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Yongqiang Sun 2019-02-26 10:52:22 -05:00 committed by Alex Deucher
parent eec3d5efd1
commit 335d5d7bbd
3 changed files with 5 additions and 6 deletions
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6
drivers/gpu/drm/amd/display/dc/dc_helper.c
View File

@ -269,7 +269,7 @@ uint32_t generic_reg_get(const struct dc_context *ctx,
} }
*/ */
uint32_t generic_reg_wait(const struct dc_context *ctx, void generic_reg_wait(const struct dc_context *ctx,
uint32_t addr, uint32_t shift, uint32_t mask, uint32_t condition_value, uint32_t addr, uint32_t shift, uint32_t mask, uint32_t condition_value,
unsigned int delay_between_poll_us, unsigned int time_out_num_tries, unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
const char *func_name, int line) const char *func_name, int line)
@ -299,7 +299,7 @@ uint32_t generic_reg_wait(const struct dc_context *ctx,
DC_LOG_DC("REG_WAIT taking a while: %dms in %s line:%d\n", DC_LOG_DC("REG_WAIT taking a while: %dms in %s line:%d\n",
delay_between_poll_us * i / 1000, delay_between_poll_us * i / 1000,
func_name, line); func_name, line);
return reg_val; return;
} }
} }
@ -309,8 +309,6 @@ uint32_t generic_reg_wait(const struct dc_context *ctx,
if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
BREAK_TO_DEBUGGER(); BREAK_TO_DEBUGGER();
return reg_val;
} }
void generic_write_indirect_reg(const struct dc_context *ctx, void generic_write_indirect_reg(const struct dc_context *ctx,

3
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
View File

@ -317,9 +317,10 @@ static enum aux_channel_operation_result get_channel_status(
*returned_bytes = 0; *returned_bytes = 0;
/* poll to make sure that SW_DONE is asserted */ /* poll to make sure that SW_DONE is asserted */
value = REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 1, REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 1,
10, aux110->timeout_period/10); 10, aux110->timeout_period/10);
value = REG_READ(AUX_SW_STATUS);
/* in case HPD is LOW, exit AUX transaction */ /* in case HPD is LOW, exit AUX transaction */
if ((value & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK)) if ((value & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK))
return AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON; return AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON;

2
drivers/gpu/drm/amd/display/dc/dm_services.h
View File

@ -159,7 +159,7 @@ uint32_t generic_reg_update_ex(const struct dc_context *ctx,
* return number of poll before condition is met * return number of poll before condition is met
* return 0 if condition is not meet after specified time out tries * return 0 if condition is not meet after specified time out tries
*/ */
unsigned int generic_reg_wait(const struct dc_context *ctx, void generic_reg_wait(const struct dc_context *ctx,
uint32_t addr, uint32_t mask, uint32_t shift, uint32_t condition_value, uint32_t addr, uint32_t mask, uint32_t shift, uint32_t condition_value,
unsigned int delay_between_poll_us, unsigned int time_out_num_tries, unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
const char *func_name, int line); const char *func_name, int line);