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arm64: dts: Add L2-cache DT node for NS2 

Recent kernels requires cache hierrachy to be defined via DT hence
this patch updates NS2 DT accordingly.

Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Sandeep Tripathy <tripathy@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This commit is contained in:
Anup Patel 2015-10-02 23:24:18 +05:30 committed by Florian Fainelli
parent 8005c49d9a
commit 33a93aa490
1 changed files with 8 additions and 0 deletions
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8
arch/arm64/boot/dts/broadcom/ns2.dtsi
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@ -50,6 +50,7 @@ cpu@0 {
reg = <0 0>; reg = <0 0>;
enable-method = "spin-table"; enable-method = "spin-table";
cpu-release-addr = <0 0x84b00000>; cpu-release-addr = <0 0x84b00000>;
next-level-cache = <&CLUSTER0_L2>;
}; };
cpu@1 { cpu@1 {
@ -58,6 +59,7 @@ cpu@1 {
reg = <0 1>; reg = <0 1>;
enable-method = "spin-table"; enable-method = "spin-table";
cpu-release-addr = <0 0x84b00000>; cpu-release-addr = <0 0x84b00000>;
next-level-cache = <&CLUSTER0_L2>;
}; };
cpu@2 { cpu@2 {
@ -66,6 +68,7 @@ cpu@2 {
reg = <0 2>; reg = <0 2>;
enable-method = "spin-table"; enable-method = "spin-table";
cpu-release-addr = <0 0x84b00000>; cpu-release-addr = <0 0x84b00000>;
next-level-cache = <&CLUSTER0_L2>;
}; };
cpu@3 { cpu@3 {
@ -74,6 +77,11 @@ cpu@3 {
reg = <0 3>; reg = <0 3>;
enable-method = "spin-table"; enable-method = "spin-table";
cpu-release-addr = <0 0x84b00000>; cpu-release-addr = <0 0x84b00000>;
next-level-cache = <&CLUSTER0_L2>;
};
CLUSTER0_L2: l2-cache@000 {
compatible = "cache";
}; };
}; };