rtlwifi: rtl8192c-common: Convert driver to use common DM table initialization
These changes convert both rtl8192ce and rtl8192cu to use the new routine. Some additional definitions are needed in the core, thus several of the headers for other drivers are affected, but no other executable code is changed. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
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@ -1878,6 +1878,7 @@ void rtl_dm_diginit(struct ieee80211_hw *hw, u32 cur_igvalue)
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struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
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dm_digtable->dig_enable_flag = true;
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dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
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dm_digtable->cur_igvalue = cur_igvalue;
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dm_digtable->pre_igvalue = 0;
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dm_digtable->cur_sta_cstate = DIG_STA_DISCONNECT;
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@ -1903,5 +1904,7 @@ void rtl_dm_diginit(struct ieee80211_hw *hw, u32 cur_igvalue)
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dm_digtable->media_connect_1 = false;
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rtlpriv->dm.dm_initialgain_enable = true;
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dm_digtable->bt30_cur_igi = 0x32;
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dm_digtable->pre_cck_pd_state = CCK_PD_STAGE_MAX;
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dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_LOWRSSI;
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}
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EXPORT_SYMBOL(rtl_dm_diginit);
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@ -46,6 +46,22 @@
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#define DM_DIG_BACKOFF_MIN -4
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#define DM_DIG_BACKOFF_DEFAULT 10
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enum cck_packet_detection_threshold {
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CCK_PD_STAGE_LOWRSSI = 0,
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CCK_PD_STAGE_HIGHRSSI = 1,
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CCK_FA_STAGE_LOW = 2,
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CCK_FA_STAGE_HIGH = 3,
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CCK_PD_STAGE_MAX = 4,
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};
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enum dm_dig_ext_port_alg_e {
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DIG_EXT_PORT_STAGE_0 = 0,
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DIG_EXT_PORT_STAGE_1 = 1,
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DIG_EXT_PORT_STAGE_2 = 2,
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DIG_EXT_PORT_STAGE_3 = 3,
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DIG_EXT_PORT_STAGE_MAX = 4,
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};
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enum dm_dig_connect_e {
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DIG_STA_DISCONNECT,
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DIG_STA_CONNECT,
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@ -249,14 +249,6 @@ enum tag_dynamic_init_gain_operation_type_definition {
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DIG_OP_TYPE_MAX
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};
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enum tag_cck_packet_detection_threshold_type_definition {
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CCK_PD_STAGE_LOWRSSI = 0,
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CCK_PD_STAGE_HIGHRSSI = 1,
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CCK_FA_STAGE_LOW = 2,
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CCK_FA_STAGE_HIGH = 3,
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CCK_PD_STAGE_MAX = 4,
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};
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enum dm_1r_cca_e {
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CCA_1R = 0,
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CCA_2R = 1,
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@ -275,14 +267,6 @@ enum dm_sw_ant_switch_e {
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ANS_ANTENNA_MAX = 3,
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};
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enum dm_dig_ext_port_alg_e {
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DIG_EXT_PORT_STAGE_0 = 0,
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DIG_EXT_PORT_STAGE_1 = 1,
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DIG_EXT_PORT_STAGE_2 = 2,
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DIG_EXT_PORT_STAGE_3 = 3,
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DIG_EXT_PORT_STAGE_MAX = 4,
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};
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enum pwr_track_control_method {
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BBSWING,
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TXAGC
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@ -195,36 +195,6 @@ void dm_savepowerindex(struct ieee80211_hw *hw)
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}
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EXPORT_SYMBOL_GPL(dm_savepowerindex);
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static void rtl92c_dm_diginit(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
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dm_digtable->dig_enable_flag = true;
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dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
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dm_digtable->cur_igvalue = 0x20;
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dm_digtable->pre_igvalue = 0x0;
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dm_digtable->cursta_cstate = DIG_STA_DISCONNECT;
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dm_digtable->presta_cstate = DIG_STA_DISCONNECT;
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dm_digtable->curmultista_cstate = DIG_MULTISTA_DISCONNECT;
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dm_digtable->rssi_lowthresh = DM_DIG_THRESH_LOW;
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dm_digtable->rssi_highthresh = DM_DIG_THRESH_HIGH;
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dm_digtable->fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
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dm_digtable->fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
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dm_digtable->rx_gain_max = DM_DIG_MAX;
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dm_digtable->rx_gain_min = DM_DIG_MIN;
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dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT;
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dm_digtable->back_range_max = DM_DIG_BACKOFF_MAX;
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dm_digtable->back_range_min = DM_DIG_BACKOFF_MIN;
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dm_digtable->pre_cck_pd_state = CCK_PD_STAGE_MAX;
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dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_LowRssi;
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dm_digtable->forbidden_igi = DM_DIG_MIN;
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dm_digtable->large_fa_hit = 0;
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dm_digtable->recover_cnt = 0;
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dm_digtable->dig_min_0 = 0x25;
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}
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static u8 rtl92c_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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@ -508,27 +478,27 @@ static void rtl92c_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
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if (dm_digtable->rssi_val_min > 100)
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dm_digtable->rssi_val_min = 100;
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if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LowRssi) {
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if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LOWRSSI) {
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if (dm_digtable->rssi_val_min <= 25)
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dm_digtable->cur_cck_pd_state =
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CCK_PD_STAGE_LowRssi;
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CCK_PD_STAGE_LOWRSSI;
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else
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dm_digtable->cur_cck_pd_state =
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CCK_PD_STAGE_HighRssi;
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CCK_PD_STAGE_HIGHRSSI;
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} else {
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if (dm_digtable->rssi_val_min <= 20)
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dm_digtable->cur_cck_pd_state =
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CCK_PD_STAGE_LowRssi;
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CCK_PD_STAGE_LOWRSSI;
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else
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dm_digtable->cur_cck_pd_state =
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CCK_PD_STAGE_HighRssi;
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CCK_PD_STAGE_HIGHRSSI;
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}
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} else {
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dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX;
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}
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if (dm_digtable->pre_cck_pd_state != dm_digtable->cur_cck_pd_state) {
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if ((dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_LowRssi) ||
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if ((dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI) ||
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(dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_MAX))
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rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x83);
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else
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@ -1375,7 +1345,7 @@ void rtl92c_dm_init(struct ieee80211_hw *hw)
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rtlpriv->dm.undec_sm_pwdb = -1;
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rtlpriv->dm.undec_sm_cck = -1;
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rtlpriv->dm.dm_initialgain_enable = true;
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rtl92c_dm_diginit(hw);
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rtl_dm_diginit(hw, 0x20);
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rtlpriv->dm.dm_flag |= HAL_DM_HIPWR_DISABLE;
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rtl92c_dm_init_dynamic_txpower(hw);
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@ -110,14 +110,6 @@ enum tag_dynamic_init_gain_operation_type_definition {
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DIG_OP_TYPE_MAX
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};
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enum tag_cck_packet_detection_threshold_type_definition {
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CCK_PD_STAGE_LowRssi = 0,
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CCK_PD_STAGE_HighRssi = 1,
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CCK_FA_STAGE_Low = 2,
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CCK_FA_STAGE_High = 3,
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CCK_PD_STAGE_MAX = 4,
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};
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enum dm_1r_cca_e {
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CCA_1R = 0,
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CCA_2R = 1,
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@ -136,14 +128,6 @@ enum dm_sw_ant_switch_e {
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ANS_ANTENNA_MAX = 3,
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};
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enum dm_dig_ext_port_alg_e {
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DIG_EXT_PORT_STAGE_0 = 0,
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DIG_EXT_PORT_STAGE_1 = 1,
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DIG_EXT_PORT_STAGE_2 = 2,
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DIG_EXT_PORT_STAGE_3 = 3,
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DIG_EXT_PORT_STAGE_MAX = 4,
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};
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void rtl92c_dm_init(struct ieee80211_hw *hw);
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void rtl92c_dm_watchdog(struct ieee80211_hw *hw);
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void rtl92c_dm_write_dig(struct ieee80211_hw *hw);
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@ -95,14 +95,6 @@ enum tag_dynamic_init_gain_operation_type_definition {
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DIG_OP_TYPE_MAX
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};
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enum tag_cck_packet_detection_threshold_type_definition {
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CCK_PD_STAGE_LOWRSSI = 0,
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CCK_PD_STAGE_HIGHRSSI = 1,
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CCK_FA_STAGE_LOW = 2,
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CCK_FA_STAGE_HIGH = 3,
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CCK_PD_STAGE_MAX = 4,
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};
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enum dm_1r_cca {
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CCA_1R = 0,
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CCA_2R = 1,
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@ -121,14 +113,6 @@ enum dm_sw_ant_switch {
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ANS_ANTENNA_MAX = 3,
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};
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enum dm_dig_ext_port_alg {
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DIG_EXT_PORT_STAGE_0 = 0,
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DIG_EXT_PORT_STAGE_1 = 1,
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DIG_EXT_PORT_STAGE_2 = 2,
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DIG_EXT_PORT_STAGE_3 = 3,
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DIG_EXT_PORT_STAGE_MAX = 4,
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};
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void rtl92d_dm_init(struct ieee80211_hw *hw);
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void rtl92d_dm_watchdog(struct ieee80211_hw *hw);
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void rtl92d_dm_init_edca_turbo(struct ieee80211_hw *hw);
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@ -54,14 +54,6 @@ enum dm_dig_sta {
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DM_STA_DIG_MAX
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};
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enum dm_dig_ext_port_alg {
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DIG_EXT_PORT_STAGE_0 = 0,
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DIG_EXT_PORT_STAGE_1 = 1,
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DIG_EXT_PORT_STAGE_2 = 2,
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DIG_EXT_PORT_STAGE_3 = 3,
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DIG_EXT_PORT_STAGE_MAX = 4,
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};
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enum dm_ratr_sta {
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DM_RATR_STA_HIGH = 0,
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DM_RATR_STA_MIDDLEHIGH = 1,
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@ -396,30 +396,30 @@ static void rtl8723e_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
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if (dm_digtable->cursta_cstate == DIG_STA_CONNECT) {
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dm_digtable->rssi_val_min = rtl8723e_dm_initial_gain_min_pwdb(hw);
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if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LowRssi) {
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if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LOWRSSI) {
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if (dm_digtable->rssi_val_min <= 25)
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dm_digtable->cur_cck_pd_state =
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CCK_PD_STAGE_LowRssi;
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CCK_PD_STAGE_LOWRSSI;
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else
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dm_digtable->cur_cck_pd_state =
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CCK_PD_STAGE_HighRssi;
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CCK_PD_STAGE_HIGHRSSI;
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} else {
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if (dm_digtable->rssi_val_min <= 20)
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dm_digtable->cur_cck_pd_state =
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CCK_PD_STAGE_LowRssi;
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CCK_PD_STAGE_LOWRSSI;
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else
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dm_digtable->cur_cck_pd_state =
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CCK_PD_STAGE_HighRssi;
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CCK_PD_STAGE_HIGHRSSI;
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}
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} else {
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dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX;
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}
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if (dm_digtable->pre_cck_pd_state != dm_digtable->cur_cck_pd_state) {
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if (dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_LowRssi) {
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if (dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI) {
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if (rtlpriv->falsealm_cnt.cnt_cck_fail > 800)
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dm_digtable->cur_cck_fa_state =
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CCK_FA_STAGE_High;
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CCK_FA_STAGE_HIGH;
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else
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dm_digtable->cur_cck_fa_state =
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CCK_FA_STAGE_LOW;
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@ -95,14 +95,6 @@ enum tag_dynamic_init_gain_operation_type_definition {
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DIG_OP_TYPE_MAX
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};
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enum tag_cck_packet_detection_threshold_type_definition {
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CCK_PD_STAGE_LowRssi = 0,
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CCK_PD_STAGE_HighRssi = 1,
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CCK_FA_STAGE_LOW = 2,
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CCK_FA_STAGE_High = 3,
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CCK_PD_STAGE_MAX = 4,
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};
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enum dm_1r_cca_e {
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CCA_1R = 0,
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CCA_2R = 1,
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ANS_ANTENNA_MAX = 3,
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};
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enum dm_dig_ext_port_alg_e {
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DIG_EXT_PORT_STAGE_0 = 0,
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DIG_EXT_PORT_STAGE_1 = 1,
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DIG_EXT_PORT_STAGE_2 = 2,
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DIG_EXT_PORT_STAGE_3 = 3,
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DIG_EXT_PORT_STAGE_MAX = 4,
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};
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#define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1)
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#define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1)
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#define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1)
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@ -239,14 +239,6 @@ enum dm_sw_ant_switch_e {
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ANS_ANTENNA_MAX = 3,
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};
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enum dm_dig_ext_port_alg_e {
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DIG_EXT_PORT_STAGE_0 = 0,
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DIG_EXT_PORT_STAGE_1 = 1,
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DIG_EXT_PORT_STAGE_2 = 2,
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DIG_EXT_PORT_STAGE_3 = 3,
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DIG_EXT_PORT_STAGE_MAX = 4,
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};
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enum pwr_track_control_method {
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BBSWING,
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TXAGC
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@ -255,14 +255,6 @@ enum tag_dynamic_init_gain_operation_type_definition {
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DIG_OP_TYPE_MAX
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};
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enum tag_cck_packet_detection_threshold_type_definition {
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CCK_PD_STAGE_LOWRSSI = 0,
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CCK_PD_STAGE_HIGHRSSI = 1,
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CCK_FA_STAGE_LOW = 2,
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CCK_FA_STAGE_HIGH = 3,
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CCK_PD_STAGE_MAX = 4,
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};
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enum dm_1r_cca_e {
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CCA_1R = 0,
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CCA_2R = 1,
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ANS_ANTENNA_MAX = 3,
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};
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enum dm_dig_ext_port_alg_e {
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DIG_EXT_PORT_STAGE_0 = 0,
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DIG_EXT_PORT_STAGE_1 = 1,
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DIG_EXT_PORT_STAGE_2 = 2,
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DIG_EXT_PORT_STAGE_3 = 3,
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DIG_EXT_PORT_STAGE_MAX = 4,
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};
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enum pwr_track_control_method {
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BBSWING,
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TXAGC,
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