drm: bridge: analogix/dp: split exynos dp driver to bridge directory
Split the dp core driver from exynos directory to bridge directory, and rename the core driver to analogix_dp_*, rename the platform code to exynos_dp. Beside the new analogix_dp driver would export six hooks. "analogix_dp_bind()" and "analogix_dp_unbind()" "analogix_dp_suspned()" and "analogix_dp_resume()" "analogix_dp_detect()" and "analogix_dp_get_modes()" The bind/unbind symbols is used for analogix platform driver to connect with analogix_dp core driver. And the detect/get_modes is used for analogix platform driver to init the connector. They reason why connector need register in helper driver is rockchip drm haven't implement the atomic API, but Exynos drm have implement it, so there would need two different connector helper functions, that's why we leave the connector register in helper driver. Acked-by: Inki Dae <inki.dae@samsung.com> Tested-by: Caesar Wang <wxt@rock-chips.com> Tested-by: Douglas Anderson <dianders@chromium.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Yakir Yang
parent
4604202ca8
commit
3424e3a4f8
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@ -40,4 +40,6 @@ config DRM_PARADE_PS8622
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---help---
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Parade eDP-LVDS bridge chip driver.
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source "drivers/gpu/drm/bridge/analogix/Kconfig"
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endmenu
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@ -4,3 +4,4 @@ obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
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obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
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obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
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obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
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obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
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@ -0,0 +1,3 @@
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config DRM_ANALOGIX_DP
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tristate
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depends on DRM
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@ -0,0 +1,2 @@
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analogix_dp-objs := analogix_dp_core.o analogix_dp_reg.o
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obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix_dp.o
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,277 @@
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/*
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* Header file for Analogix DP (Display Port) core interface driver.
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*
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* Copyright (C) 2012 Samsung Electronics Co., Ltd.
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* Author: Jingoo Han <jg1.han@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef _ANALOGIX_DP_CORE_H
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#define _ANALOGIX_DP_CORE_H
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#include <drm/drm_crtc.h>
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#include <drm/drm_dp_helper.h>
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#define DP_TIMEOUT_LOOP_COUNT 100
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#define MAX_CR_LOOP 5
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#define MAX_EQ_LOOP 5
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enum link_rate_type {
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LINK_RATE_1_62GBPS = 0x06,
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LINK_RATE_2_70GBPS = 0x0a
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};
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enum link_lane_count_type {
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LANE_COUNT1 = 1,
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LANE_COUNT2 = 2,
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LANE_COUNT4 = 4
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};
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enum link_training_state {
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START,
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CLOCK_RECOVERY,
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EQUALIZER_TRAINING,
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FINISHED,
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FAILED
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};
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enum voltage_swing_level {
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VOLTAGE_LEVEL_0,
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VOLTAGE_LEVEL_1,
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VOLTAGE_LEVEL_2,
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VOLTAGE_LEVEL_3,
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};
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enum pre_emphasis_level {
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PRE_EMPHASIS_LEVEL_0,
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PRE_EMPHASIS_LEVEL_1,
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PRE_EMPHASIS_LEVEL_2,
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PRE_EMPHASIS_LEVEL_3,
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};
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enum pattern_set {
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PRBS7,
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D10_2,
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TRAINING_PTN1,
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TRAINING_PTN2,
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DP_NONE
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};
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enum color_space {
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COLOR_RGB,
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COLOR_YCBCR422,
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COLOR_YCBCR444
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};
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enum color_depth {
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COLOR_6,
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COLOR_8,
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COLOR_10,
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COLOR_12
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};
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enum color_coefficient {
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COLOR_YCBCR601,
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COLOR_YCBCR709
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};
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enum dynamic_range {
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VESA,
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CEA
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};
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enum pll_status {
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PLL_UNLOCKED,
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PLL_LOCKED
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};
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enum clock_recovery_m_value_type {
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CALCULATED_M,
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REGISTER_M
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};
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enum video_timing_recognition_type {
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VIDEO_TIMING_FROM_CAPTURE,
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VIDEO_TIMING_FROM_REGISTER
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};
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enum analog_power_block {
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AUX_BLOCK,
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CH0_BLOCK,
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CH1_BLOCK,
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CH2_BLOCK,
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CH3_BLOCK,
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ANALOG_TOTAL,
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POWER_ALL
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};
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enum dp_irq_type {
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DP_IRQ_TYPE_HP_CABLE_IN,
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DP_IRQ_TYPE_HP_CABLE_OUT,
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DP_IRQ_TYPE_HP_CHANGE,
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DP_IRQ_TYPE_UNKNOWN,
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};
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struct video_info {
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char *name;
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bool h_sync_polarity;
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bool v_sync_polarity;
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bool interlaced;
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enum color_space color_space;
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enum dynamic_range dynamic_range;
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enum color_coefficient ycbcr_coeff;
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enum color_depth color_depth;
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enum link_rate_type link_rate;
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enum link_lane_count_type lane_count;
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};
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struct link_train {
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int eq_loop;
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int cr_loop[4];
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u8 link_rate;
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u8 lane_count;
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u8 training_lane[4];
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enum link_training_state lt_state;
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};
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struct analogix_dp_device {
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struct drm_encoder *encoder;
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struct device *dev;
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struct drm_device *drm_dev;
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struct drm_connector connector;
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struct drm_bridge *bridge;
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struct clk *clock;
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unsigned int irq;
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void __iomem *reg_base;
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struct video_info *video_info;
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struct link_train link_train;
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struct work_struct hotplug_work;
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struct phy *phy;
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int dpms_mode;
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int hpd_gpio;
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struct analogix_dp_plat_data *plat_data;
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};
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/* analogix_dp_reg.c */
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void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable);
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void analogix_dp_stop_video(struct analogix_dp_device *dp);
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void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable);
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void analogix_dp_init_analog_param(struct analogix_dp_device *dp);
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void analogix_dp_init_interrupt(struct analogix_dp_device *dp);
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void analogix_dp_reset(struct analogix_dp_device *dp);
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void analogix_dp_swreset(struct analogix_dp_device *dp);
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void analogix_dp_config_interrupt(struct analogix_dp_device *dp);
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enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp);
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void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable);
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void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
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enum analog_power_block block,
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bool enable);
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void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
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void analogix_dp_init_hpd(struct analogix_dp_device *dp);
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enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
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void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
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void analogix_dp_reset_aux(struct analogix_dp_device *dp);
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void analogix_dp_init_aux(struct analogix_dp_device *dp);
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int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp);
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void analogix_dp_enable_sw_function(struct analogix_dp_device *dp);
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int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp);
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int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
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unsigned int reg_addr,
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unsigned char data);
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int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
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unsigned int reg_addr,
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unsigned char *data);
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int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
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unsigned int reg_addr,
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unsigned int count,
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unsigned char data[]);
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int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
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unsigned int reg_addr,
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unsigned int count,
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unsigned char data[]);
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int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
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unsigned int device_addr,
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unsigned int reg_addr);
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int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
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unsigned int device_addr,
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unsigned int reg_addr,
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unsigned int *data);
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int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
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unsigned int device_addr,
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unsigned int reg_addr,
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unsigned int count,
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unsigned char edid[]);
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void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype);
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void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype);
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void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count);
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void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count);
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void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable);
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void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
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enum pattern_set pattern);
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void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level);
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void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level);
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void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level);
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void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level);
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void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
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u32 training_lane);
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void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
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u32 training_lane);
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void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
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u32 training_lane);
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void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
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u32 training_lane);
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u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp);
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u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp);
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u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp);
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u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp);
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void analogix_dp_reset_macro(struct analogix_dp_device *dp);
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void analogix_dp_init_video(struct analogix_dp_device *dp);
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void analogix_dp_set_video_color_format(struct analogix_dp_device *dp);
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int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp);
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void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
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enum clock_recovery_m_value_type type,
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u32 m_value,
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u32 n_value);
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void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type);
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void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable);
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void analogix_dp_start_video(struct analogix_dp_device *dp);
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int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
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void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
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void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
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void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
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/* I2C EDID Chip ID, Slave Address */
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#define I2C_EDID_DEVICE_ADDR 0x50
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#define I2C_E_EDID_DEVICE_ADDR 0x30
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#define EDID_BLOCK_LENGTH 0x80
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#define EDID_HEADER_PATTERN 0x00
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#define EDID_EXTENSION_FLAG 0x7e
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#define EDID_CHECKSUM 0x7f
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/* DP_MAX_LANE_COUNT */
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#define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
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#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
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/* DP_LANE_COUNT_SET */
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#define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
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/* DP_TRAINING_LANE0_SET */
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#define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
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#define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
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#define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
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#define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
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#endif /* _ANALOGIX_DP_CORE_H */
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@ -1,5 +1,5 @@
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/*
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* Samsung DP (Display port) register interface driver.
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* Analogix DP (Display port) core register interface driver.
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*
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* Copyright (C) 2012 Samsung Electronics Co., Ltd.
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* Author: Jingoo Han <jg1.han@samsung.com>
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@ -15,8 +15,8 @@
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#include <linux/delay.h>
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#include <linux/gpio.h>
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#include "exynos_dp_core.h"
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#include "exynos_dp_reg.h"
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#include "analogix_dp_core.h"
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#include "analogix_dp_reg.h"
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#define COMMON_INT_MASK_1 0
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#define COMMON_INT_MASK_2 0
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@ -24,7 +24,7 @@
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#define COMMON_INT_MASK_4 (HOTPLUG_CHG | HPD_LOST | PLUG)
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#define INT_STA_MASK INT_HPD
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void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable)
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void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable)
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{
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u32 reg;
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@ -39,7 +39,7 @@ void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable)
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}
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}
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void exynos_dp_stop_video(struct exynos_dp_device *dp)
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void analogix_dp_stop_video(struct analogix_dp_device *dp)
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{
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u32 reg;
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@ -48,7 +48,7 @@ void exynos_dp_stop_video(struct exynos_dp_device *dp)
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writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
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}
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void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable)
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void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
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{
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u32 reg;
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@ -62,7 +62,7 @@ void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable)
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writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP);
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}
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void exynos_dp_init_analog_param(struct exynos_dp_device *dp)
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void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
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{
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u32 reg;
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@ -84,7 +84,7 @@ void exynos_dp_init_analog_param(struct exynos_dp_device *dp)
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writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL);
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}
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void exynos_dp_init_interrupt(struct exynos_dp_device *dp)
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void analogix_dp_init_interrupt(struct analogix_dp_device *dp)
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{
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/* Set interrupt pin assertion polarity as high */
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writel(INT_POL1 | INT_POL0, dp->reg_base + EXYNOS_DP_INT_CTL);
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@ -104,12 +104,12 @@ void exynos_dp_init_interrupt(struct exynos_dp_device *dp)
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writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
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}
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void exynos_dp_reset(struct exynos_dp_device *dp)
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void analogix_dp_reset(struct analogix_dp_device *dp)
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{
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u32 reg;
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exynos_dp_stop_video(dp);
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exynos_dp_enable_video_mute(dp, 0);
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analogix_dp_stop_video(dp);
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analogix_dp_enable_video_mute(dp, 0);
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reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
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AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
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@ -123,7 +123,7 @@ void exynos_dp_reset(struct exynos_dp_device *dp)
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usleep_range(20, 30);
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exynos_dp_lane_swap(dp, 0);
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analogix_dp_lane_swap(dp, 0);
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writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
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writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
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@ -149,12 +149,12 @@ void exynos_dp_reset(struct exynos_dp_device *dp)
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writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
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}
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void exynos_dp_swreset(struct exynos_dp_device *dp)
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void analogix_dp_swreset(struct analogix_dp_device *dp)
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{
|
||||
writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET);
|
||||
}
|
||||
|
||||
void exynos_dp_config_interrupt(struct exynos_dp_device *dp)
|
||||
void analogix_dp_config_interrupt(struct analogix_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -175,7 +175,7 @@ void exynos_dp_config_interrupt(struct exynos_dp_device *dp)
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
|
||||
}
|
||||
|
||||
enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp)
|
||||
enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -186,7 +186,7 @@ enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp)
|
|||
return PLL_UNLOCKED;
|
||||
}
|
||||
|
||||
void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
|
||||
void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -201,7 +201,7 @@ void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
|
|||
}
|
||||
}
|
||||
|
||||
void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
|
||||
void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
|
||||
enum analog_power_block block,
|
||||
bool enable)
|
||||
{
|
||||
|
|
@ -288,12 +288,12 @@ void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
|
|||
}
|
||||
}
|
||||
|
||||
void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
|
||||
void analogix_dp_init_analog_func(struct analogix_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
int timeout_loop = 0;
|
||||
|
||||
exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
|
||||
analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
|
||||
|
||||
reg = PLL_LOCK_CHG;
|
||||
writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
|
||||
|
|
@ -303,10 +303,10 @@ void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL);
|
||||
|
||||
/* Power up PLL */
|
||||
if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
|
||||
exynos_dp_set_pll_power_down(dp, 0);
|
||||
if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
|
||||
analogix_dp_set_pll_power_down(dp, 0);
|
||||
|
||||
while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
|
||||
while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
|
||||
timeout_loop++;
|
||||
if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
|
||||
dev_err(dp->dev, "failed to get pll lock status\n");
|
||||
|
|
@ -323,7 +323,7 @@ void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
|
||||
}
|
||||
|
||||
void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp)
|
||||
void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -337,21 +337,21 @@ void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp)
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
|
||||
}
|
||||
|
||||
void exynos_dp_init_hpd(struct exynos_dp_device *dp)
|
||||
void analogix_dp_init_hpd(struct analogix_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
if (gpio_is_valid(dp->hpd_gpio))
|
||||
return;
|
||||
|
||||
exynos_dp_clear_hotplug_interrupts(dp);
|
||||
analogix_dp_clear_hotplug_interrupts(dp);
|
||||
|
||||
reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
|
||||
reg &= ~(F_HPD | HPD_CTRL);
|
||||
writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
|
||||
}
|
||||
|
||||
enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp)
|
||||
enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -378,7 +378,7 @@ enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp)
|
|||
}
|
||||
}
|
||||
|
||||
void exynos_dp_reset_aux(struct exynos_dp_device *dp)
|
||||
void analogix_dp_reset_aux(struct analogix_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -388,7 +388,7 @@ void exynos_dp_reset_aux(struct exynos_dp_device *dp)
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
|
||||
}
|
||||
|
||||
void exynos_dp_init_aux(struct exynos_dp_device *dp)
|
||||
void analogix_dp_init_aux(struct analogix_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -396,7 +396,7 @@ void exynos_dp_init_aux(struct exynos_dp_device *dp)
|
|||
reg = RPLY_RECEIV | AUX_ERR;
|
||||
writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
|
||||
|
||||
exynos_dp_reset_aux(dp);
|
||||
analogix_dp_reset_aux(dp);
|
||||
|
||||
/* Disable AUX transaction H/W retry */
|
||||
reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
|
||||
|
|
@ -413,7 +413,7 @@ void exynos_dp_init_aux(struct exynos_dp_device *dp)
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
|
||||
}
|
||||
|
||||
int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp)
|
||||
int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -429,7 +429,7 @@ int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
void exynos_dp_enable_sw_function(struct exynos_dp_device *dp)
|
||||
void analogix_dp_enable_sw_function(struct analogix_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -438,7 +438,7 @@ void exynos_dp_enable_sw_function(struct exynos_dp_device *dp)
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
|
||||
}
|
||||
|
||||
int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
|
||||
int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
|
||||
{
|
||||
int reg;
|
||||
int retval = 0;
|
||||
|
|
@ -482,7 +482,7 @@ int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
|
|||
return retval;
|
||||
}
|
||||
|
||||
int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
|
||||
int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
|
||||
unsigned int reg_addr,
|
||||
unsigned char data)
|
||||
{
|
||||
|
|
@ -516,7 +516,7 @@ int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
|
||||
|
||||
/* Start AUX transaction */
|
||||
retval = exynos_dp_start_aux_transaction(dp);
|
||||
retval = analogix_dp_start_aux_transaction(dp);
|
||||
if (retval == 0)
|
||||
break;
|
||||
else
|
||||
|
|
@ -527,7 +527,7 @@ int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
|
|||
return retval;
|
||||
}
|
||||
|
||||
int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
|
||||
int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
|
||||
unsigned int reg_addr,
|
||||
unsigned char *data)
|
||||
{
|
||||
|
|
@ -557,7 +557,7 @@ int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
|
||||
|
||||
/* Start AUX transaction */
|
||||
retval = exynos_dp_start_aux_transaction(dp);
|
||||
retval = analogix_dp_start_aux_transaction(dp);
|
||||
if (retval == 0)
|
||||
break;
|
||||
else
|
||||
|
|
@ -572,7 +572,7 @@ int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
|
|||
return retval;
|
||||
}
|
||||
|
||||
int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
|
||||
int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
|
||||
unsigned int reg_addr,
|
||||
unsigned int count,
|
||||
unsigned char data[])
|
||||
|
|
@ -622,7 +622,7 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
|
||||
|
||||
/* Start AUX transaction */
|
||||
retval = exynos_dp_start_aux_transaction(dp);
|
||||
retval = analogix_dp_start_aux_transaction(dp);
|
||||
if (retval == 0)
|
||||
break;
|
||||
else
|
||||
|
|
@ -636,7 +636,7 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
|
|||
return retval;
|
||||
}
|
||||
|
||||
int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
|
||||
int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
|
||||
unsigned int reg_addr,
|
||||
unsigned int count,
|
||||
unsigned char data[])
|
||||
|
|
@ -680,7 +680,7 @@ int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
|
||||
|
||||
/* Start AUX transaction */
|
||||
retval = exynos_dp_start_aux_transaction(dp);
|
||||
retval = analogix_dp_start_aux_transaction(dp);
|
||||
if (retval == 0)
|
||||
break;
|
||||
else
|
||||
|
|
@ -702,7 +702,7 @@ int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
|
|||
return retval;
|
||||
}
|
||||
|
||||
int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
|
||||
int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
|
||||
unsigned int device_addr,
|
||||
unsigned int reg_addr)
|
||||
{
|
||||
|
|
@ -728,14 +728,14 @@ int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
|
||||
|
||||
/* Start AUX transaction */
|
||||
retval = exynos_dp_start_aux_transaction(dp);
|
||||
retval = analogix_dp_start_aux_transaction(dp);
|
||||
if (retval != 0)
|
||||
dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
|
||||
int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
|
||||
unsigned int device_addr,
|
||||
unsigned int reg_addr,
|
||||
unsigned int *data)
|
||||
|
|
@ -750,7 +750,7 @@ int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
|
||||
|
||||
/* Select EDID device */
|
||||
retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr);
|
||||
retval = analogix_dp_select_i2c_device(dp, device_addr, reg_addr);
|
||||
if (retval != 0)
|
||||
continue;
|
||||
|
||||
|
|
@ -764,7 +764,7 @@ int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
|
||||
|
||||
/* Start AUX transaction */
|
||||
retval = exynos_dp_start_aux_transaction(dp);
|
||||
retval = analogix_dp_start_aux_transaction(dp);
|
||||
if (retval == 0)
|
||||
break;
|
||||
else
|
||||
|
|
@ -779,7 +779,7 @@ int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
|
|||
return retval;
|
||||
}
|
||||
|
||||
int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
|
||||
int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
|
||||
unsigned int device_addr,
|
||||
unsigned int reg_addr,
|
||||
unsigned int count,
|
||||
|
|
@ -807,7 +807,7 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
|
|||
* request without sending address
|
||||
*/
|
||||
if (!defer)
|
||||
retval = exynos_dp_select_i2c_device(dp,
|
||||
retval = analogix_dp_select_i2c_device(dp,
|
||||
device_addr, reg_addr + i);
|
||||
else
|
||||
defer = 0;
|
||||
|
|
@ -825,7 +825,7 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
|
|||
EXYNOS_DP_AUX_CH_CTL_1);
|
||||
|
||||
/* Start AUX transaction */
|
||||
retval = exynos_dp_start_aux_transaction(dp);
|
||||
retval = analogix_dp_start_aux_transaction(dp);
|
||||
if (retval == 0)
|
||||
break;
|
||||
else
|
||||
|
|
@ -852,7 +852,7 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
|
|||
return retval;
|
||||
}
|
||||
|
||||
void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype)
|
||||
void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -861,7 +861,7 @@ void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype)
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET);
|
||||
}
|
||||
|
||||
void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype)
|
||||
void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -869,7 +869,7 @@ void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype)
|
|||
*bwtype = reg;
|
||||
}
|
||||
|
||||
void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count)
|
||||
void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -877,7 +877,7 @@ void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count)
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
|
||||
}
|
||||
|
||||
void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count)
|
||||
void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -885,7 +885,7 @@ void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count)
|
|||
*count = reg;
|
||||
}
|
||||
|
||||
void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
|
||||
void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -900,8 +900,8 @@ void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
|
|||
}
|
||||
}
|
||||
|
||||
void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
|
||||
enum pattern_set pattern)
|
||||
void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
|
||||
enum pattern_set pattern)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -933,7 +933,7 @@ void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
|
|||
}
|
||||
}
|
||||
|
||||
void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level)
|
||||
void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -943,7 +943,7 @@ void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level)
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
|
||||
}
|
||||
|
||||
void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level)
|
||||
void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -953,7 +953,7 @@ void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level)
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
|
||||
}
|
||||
|
||||
void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level)
|
||||
void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -963,7 +963,7 @@ void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level)
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
|
||||
}
|
||||
|
||||
void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
|
||||
void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -973,7 +973,7 @@ void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
|
||||
}
|
||||
|
||||
void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
|
||||
void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
|
||||
u32 training_lane)
|
||||
{
|
||||
u32 reg;
|
||||
|
|
@ -982,7 +982,7 @@ void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
|
||||
}
|
||||
|
||||
void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
|
||||
void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
|
||||
u32 training_lane)
|
||||
{
|
||||
u32 reg;
|
||||
|
|
@ -991,8 +991,8 @@ void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
|
||||
}
|
||||
|
||||
void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
|
||||
u32 training_lane)
|
||||
void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
|
||||
u32 training_lane)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -1000,7 +1000,7 @@ void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
|
||||
}
|
||||
|
||||
void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
|
||||
void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
|
||||
u32 training_lane)
|
||||
{
|
||||
u32 reg;
|
||||
|
|
@ -1009,7 +1009,7 @@ void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
|
||||
}
|
||||
|
||||
u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp)
|
||||
u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -1017,7 +1017,7 @@ u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp)
|
|||
return reg;
|
||||
}
|
||||
|
||||
u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp)
|
||||
u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -1025,7 +1025,7 @@ u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp)
|
|||
return reg;
|
||||
}
|
||||
|
||||
u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp)
|
||||
u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -1033,7 +1033,7 @@ u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp)
|
|||
return reg;
|
||||
}
|
||||
|
||||
u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp)
|
||||
u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -1041,7 +1041,7 @@ u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp)
|
|||
return reg;
|
||||
}
|
||||
|
||||
void exynos_dp_reset_macro(struct exynos_dp_device *dp)
|
||||
void analogix_dp_reset_macro(struct analogix_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -1056,7 +1056,7 @@ void exynos_dp_reset_macro(struct exynos_dp_device *dp)
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
|
||||
}
|
||||
|
||||
void exynos_dp_init_video(struct exynos_dp_device *dp)
|
||||
void analogix_dp_init_video(struct analogix_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -1076,7 +1076,7 @@ void exynos_dp_init_video(struct exynos_dp_device *dp)
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8);
|
||||
}
|
||||
|
||||
void exynos_dp_set_video_color_format(struct exynos_dp_device *dp)
|
||||
void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -1096,7 +1096,7 @@ void exynos_dp_set_video_color_format(struct exynos_dp_device *dp)
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
|
||||
}
|
||||
|
||||
int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
|
||||
int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -1124,7 +1124,7 @@ int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
|
|||
return 0;
|
||||
}
|
||||
|
||||
void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
|
||||
void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
|
||||
enum clock_recovery_m_value_type type,
|
||||
u32 m_value,
|
||||
u32 n_value)
|
||||
|
|
@ -1159,7 +1159,7 @@ void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
|
|||
}
|
||||
}
|
||||
|
||||
void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type)
|
||||
void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -1174,7 +1174,7 @@ void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type)
|
|||
}
|
||||
}
|
||||
|
||||
void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable)
|
||||
void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -1191,7 +1191,7 @@ void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable)
|
|||
}
|
||||
}
|
||||
|
||||
void exynos_dp_start_video(struct exynos_dp_device *dp)
|
||||
void analogix_dp_start_video(struct analogix_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -1200,7 +1200,7 @@ void exynos_dp_start_video(struct exynos_dp_device *dp)
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
|
||||
}
|
||||
|
||||
int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp)
|
||||
int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -1216,7 +1216,7 @@ int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp)
|
|||
return 0;
|
||||
}
|
||||
|
||||
void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp)
|
||||
void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -1244,7 +1244,7 @@ void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp)
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
|
||||
}
|
||||
|
||||
void exynos_dp_enable_scrambling(struct exynos_dp_device *dp)
|
||||
void analogix_dp_enable_scrambling(struct analogix_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -1253,7 +1253,7 @@ void exynos_dp_enable_scrambling(struct exynos_dp_device *dp)
|
|||
writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
|
||||
}
|
||||
|
||||
void exynos_dp_disable_scrambling(struct exynos_dp_device *dp)
|
||||
void analogix_dp_disable_scrambling(struct analogix_dp_device *dp)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Register definition file for Samsung DP driver
|
||||
* Register definition file for Analogix DP core driver
|
||||
*
|
||||
* Copyright (C) 2012 Samsung Electronics Co., Ltd.
|
||||
* Author: Jingoo Han <jg1.han@samsung.com>
|
||||
|
|
@ -9,8 +9,8 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _EXYNOS_DP_REG_H
|
||||
#define _EXYNOS_DP_REG_H
|
||||
#ifndef _ANALOGIX_DP_REG_H
|
||||
#define _ANALOGIX_DP_REG_H
|
||||
|
||||
#define EXYNOS_DP_TX_SW_RESET 0x14
|
||||
#define EXYNOS_DP_FUNC_EN_1 0x18
|
||||
|
|
@ -363,4 +363,4 @@
|
|||
#define VIDEO_MODE_SLAVE_MODE (0x1 << 0)
|
||||
#define VIDEO_MODE_MASTER_MODE (0x0 << 0)
|
||||
|
||||
#endif /* _EXYNOS_DP_REG_H */
|
||||
#endif /* _ANALOGIX_DP_REG_H */
|
||||
|
|
@ -71,8 +71,9 @@ config DRM_EXYNOS_DSI
|
|||
This enables support for Exynos MIPI-DSI device.
|
||||
|
||||
config DRM_EXYNOS_DP
|
||||
bool "Display Port"
|
||||
bool "EXYNOS specific extensions for Analogix DP driver"
|
||||
depends on DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON
|
||||
select DRM_ANALOGIX_DP
|
||||
default DRM_EXYNOS
|
||||
select DRM_PANEL
|
||||
help
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ exynosdrm-$(CONFIG_DRM_EXYNOS5433_DECON) += exynos5433_drm_decon.o
|
|||
exynosdrm-$(CONFIG_DRM_EXYNOS7_DECON) += exynos7_drm_decon.o
|
||||
exynosdrm-$(CONFIG_DRM_EXYNOS_DPI) += exynos_drm_dpi.o
|
||||
exynosdrm-$(CONFIG_DRM_EXYNOS_DSI) += exynos_drm_dsi.o
|
||||
exynosdrm-$(CONFIG_DRM_EXYNOS_DP) += exynos_dp_core.o exynos_dp_reg.o
|
||||
exynosdrm-$(CONFIG_DRM_EXYNOS_DP) += exynos_dp_core.o
|
||||
exynosdrm-$(CONFIG_DRM_EXYNOS_MIXER) += exynos_mixer.o
|
||||
exynosdrm-$(CONFIG_DRM_EXYNOS_HDMI) += exynos_hdmi.o
|
||||
exynosdrm-$(CONFIG_DRM_EXYNOS_VIDI) += exynos_drm_vidi.o
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,282 +0,0 @@
|
|||
/*
|
||||
* Header file for Samsung DP (Display Port) interface driver.
|
||||
*
|
||||
* Copyright (C) 2012 Samsung Electronics Co., Ltd.
|
||||
* Author: Jingoo Han <jg1.han@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef _EXYNOS_DP_CORE_H
|
||||
#define _EXYNOS_DP_CORE_H
|
||||
|
||||
#include <drm/drm_crtc.h>
|
||||
#include <drm/drm_dp_helper.h>
|
||||
#include <drm/exynos_drm.h>
|
||||
#include <video/videomode.h>
|
||||
|
||||
#include "exynos_drm_drv.h"
|
||||
|
||||
#define DP_TIMEOUT_LOOP_COUNT 100
|
||||
#define MAX_CR_LOOP 5
|
||||
#define MAX_EQ_LOOP 5
|
||||
|
||||
enum link_rate_type {
|
||||
LINK_RATE_1_62GBPS = 0x06,
|
||||
LINK_RATE_2_70GBPS = 0x0a
|
||||
};
|
||||
|
||||
enum link_lane_count_type {
|
||||
LANE_COUNT1 = 1,
|
||||
LANE_COUNT2 = 2,
|
||||
LANE_COUNT4 = 4
|
||||
};
|
||||
|
||||
enum link_training_state {
|
||||
START,
|
||||
CLOCK_RECOVERY,
|
||||
EQUALIZER_TRAINING,
|
||||
FINISHED,
|
||||
FAILED
|
||||
};
|
||||
|
||||
enum voltage_swing_level {
|
||||
VOLTAGE_LEVEL_0,
|
||||
VOLTAGE_LEVEL_1,
|
||||
VOLTAGE_LEVEL_2,
|
||||
VOLTAGE_LEVEL_3,
|
||||
};
|
||||
|
||||
enum pre_emphasis_level {
|
||||
PRE_EMPHASIS_LEVEL_0,
|
||||
PRE_EMPHASIS_LEVEL_1,
|
||||
PRE_EMPHASIS_LEVEL_2,
|
||||
PRE_EMPHASIS_LEVEL_3,
|
||||
};
|
||||
|
||||
enum pattern_set {
|
||||
PRBS7,
|
||||
D10_2,
|
||||
TRAINING_PTN1,
|
||||
TRAINING_PTN2,
|
||||
DP_NONE
|
||||
};
|
||||
|
||||
enum color_space {
|
||||
COLOR_RGB,
|
||||
COLOR_YCBCR422,
|
||||
COLOR_YCBCR444
|
||||
};
|
||||
|
||||
enum color_depth {
|
||||
COLOR_6,
|
||||
COLOR_8,
|
||||
COLOR_10,
|
||||
COLOR_12
|
||||
};
|
||||
|
||||
enum color_coefficient {
|
||||
COLOR_YCBCR601,
|
||||
COLOR_YCBCR709
|
||||
};
|
||||
|
||||
enum dynamic_range {
|
||||
VESA,
|
||||
CEA
|
||||
};
|
||||
|
||||
enum pll_status {
|
||||
PLL_UNLOCKED,
|
||||
PLL_LOCKED
|
||||
};
|
||||
|
||||
enum clock_recovery_m_value_type {
|
||||
CALCULATED_M,
|
||||
REGISTER_M
|
||||
};
|
||||
|
||||
enum video_timing_recognition_type {
|
||||
VIDEO_TIMING_FROM_CAPTURE,
|
||||
VIDEO_TIMING_FROM_REGISTER
|
||||
};
|
||||
|
||||
enum analog_power_block {
|
||||
AUX_BLOCK,
|
||||
CH0_BLOCK,
|
||||
CH1_BLOCK,
|
||||
CH2_BLOCK,
|
||||
CH3_BLOCK,
|
||||
ANALOG_TOTAL,
|
||||
POWER_ALL
|
||||
};
|
||||
|
||||
enum dp_irq_type {
|
||||
DP_IRQ_TYPE_HP_CABLE_IN,
|
||||
DP_IRQ_TYPE_HP_CABLE_OUT,
|
||||
DP_IRQ_TYPE_HP_CHANGE,
|
||||
DP_IRQ_TYPE_UNKNOWN,
|
||||
};
|
||||
|
||||
struct video_info {
|
||||
char *name;
|
||||
|
||||
bool h_sync_polarity;
|
||||
bool v_sync_polarity;
|
||||
bool interlaced;
|
||||
|
||||
enum color_space color_space;
|
||||
enum dynamic_range dynamic_range;
|
||||
enum color_coefficient ycbcr_coeff;
|
||||
enum color_depth color_depth;
|
||||
|
||||
enum link_rate_type link_rate;
|
||||
enum link_lane_count_type lane_count;
|
||||
};
|
||||
|
||||
struct link_train {
|
||||
int eq_loop;
|
||||
int cr_loop[4];
|
||||
|
||||
u8 link_rate;
|
||||
u8 lane_count;
|
||||
u8 training_lane[4];
|
||||
|
||||
enum link_training_state lt_state;
|
||||
};
|
||||
|
||||
struct exynos_dp_device {
|
||||
struct drm_encoder encoder;
|
||||
struct device *dev;
|
||||
struct drm_device *drm_dev;
|
||||
struct drm_connector connector;
|
||||
struct drm_panel *panel;
|
||||
struct drm_bridge *bridge;
|
||||
struct drm_bridge *ptn_bridge;
|
||||
struct clk *clock;
|
||||
unsigned int irq;
|
||||
void __iomem *reg_base;
|
||||
|
||||
struct video_info *video_info;
|
||||
struct link_train link_train;
|
||||
struct work_struct hotplug_work;
|
||||
struct phy *phy;
|
||||
int dpms_mode;
|
||||
int hpd_gpio;
|
||||
struct videomode vm;
|
||||
};
|
||||
|
||||
/* exynos_dp_reg.c */
|
||||
void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable);
|
||||
void exynos_dp_stop_video(struct exynos_dp_device *dp);
|
||||
void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable);
|
||||
void exynos_dp_init_analog_param(struct exynos_dp_device *dp);
|
||||
void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
|
||||
void exynos_dp_reset(struct exynos_dp_device *dp);
|
||||
void exynos_dp_swreset(struct exynos_dp_device *dp);
|
||||
void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
|
||||
enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
|
||||
void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
|
||||
void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
|
||||
enum analog_power_block block,
|
||||
bool enable);
|
||||
void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
|
||||
void exynos_dp_init_hpd(struct exynos_dp_device *dp);
|
||||
enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp);
|
||||
void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp);
|
||||
void exynos_dp_reset_aux(struct exynos_dp_device *dp);
|
||||
void exynos_dp_init_aux(struct exynos_dp_device *dp);
|
||||
int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
|
||||
void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
|
||||
int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
|
||||
int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
|
||||
unsigned int reg_addr,
|
||||
unsigned char data);
|
||||
int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
|
||||
unsigned int reg_addr,
|
||||
unsigned char *data);
|
||||
int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
|
||||
unsigned int reg_addr,
|
||||
unsigned int count,
|
||||
unsigned char data[]);
|
||||
int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
|
||||
unsigned int reg_addr,
|
||||
unsigned int count,
|
||||
unsigned char data[]);
|
||||
int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
|
||||
unsigned int device_addr,
|
||||
unsigned int reg_addr);
|
||||
int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
|
||||
unsigned int device_addr,
|
||||
unsigned int reg_addr,
|
||||
unsigned int *data);
|
||||
int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
|
||||
unsigned int device_addr,
|
||||
unsigned int reg_addr,
|
||||
unsigned int count,
|
||||
unsigned char edid[]);
|
||||
void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
|
||||
void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
|
||||
void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
|
||||
void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
|
||||
void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
|
||||
void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
|
||||
enum pattern_set pattern);
|
||||
void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
|
||||
void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
|
||||
void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
|
||||
void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
|
||||
void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
|
||||
u32 training_lane);
|
||||
void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
|
||||
u32 training_lane);
|
||||
void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
|
||||
u32 training_lane);
|
||||
void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
|
||||
u32 training_lane);
|
||||
u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
|
||||
u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
|
||||
u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
|
||||
u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
|
||||
void exynos_dp_reset_macro(struct exynos_dp_device *dp);
|
||||
void exynos_dp_init_video(struct exynos_dp_device *dp);
|
||||
|
||||
void exynos_dp_set_video_color_format(struct exynos_dp_device *dp);
|
||||
int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
|
||||
void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
|
||||
enum clock_recovery_m_value_type type,
|
||||
u32 m_value,
|
||||
u32 n_value);
|
||||
void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
|
||||
void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
|
||||
void exynos_dp_start_video(struct exynos_dp_device *dp);
|
||||
int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
|
||||
void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp);
|
||||
void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
|
||||
void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
|
||||
|
||||
/* I2C EDID Chip ID, Slave Address */
|
||||
#define I2C_EDID_DEVICE_ADDR 0x50
|
||||
#define I2C_E_EDID_DEVICE_ADDR 0x30
|
||||
|
||||
#define EDID_BLOCK_LENGTH 0x80
|
||||
#define EDID_HEADER_PATTERN 0x00
|
||||
#define EDID_EXTENSION_FLAG 0x7e
|
||||
#define EDID_CHECKSUM 0x7f
|
||||
|
||||
/* DP_MAX_LANE_COUNT */
|
||||
#define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
|
||||
#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
|
||||
|
||||
/* DP_LANE_COUNT_SET */
|
||||
#define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
|
||||
|
||||
/* DP_TRAINING_LANE0_SET */
|
||||
#define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
|
||||
#define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
|
||||
#define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
|
||||
#define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
|
||||
|
||||
#endif /* _EXYNOS_DP_CORE_H */
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* Analogix DP (Display Port) Core interface driver.
|
||||
*
|
||||
* Copyright (C) 2015 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
#ifndef _ANALOGIX_DP_H_
|
||||
#define _ANALOGIX_DP_H_
|
||||
|
||||
#include <drm/drm_crtc.h>
|
||||
|
||||
enum analogix_dp_devtype {
|
||||
EXYNOS_DP,
|
||||
};
|
||||
|
||||
struct analogix_dp_plat_data {
|
||||
enum analogix_dp_devtype dev_type;
|
||||
struct drm_panel *panel;
|
||||
struct drm_encoder *encoder;
|
||||
struct drm_connector *connector;
|
||||
|
||||
int (*power_on)(struct analogix_dp_plat_data *);
|
||||
int (*power_off)(struct analogix_dp_plat_data *);
|
||||
int (*attach)(struct analogix_dp_plat_data *, struct drm_bridge *,
|
||||
struct drm_connector *);
|
||||
int (*get_modes)(struct analogix_dp_plat_data *);
|
||||
};
|
||||
|
||||
int analogix_dp_resume(struct device *dev);
|
||||
int analogix_dp_suspend(struct device *dev);
|
||||
|
||||
int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
|
||||
struct analogix_dp_plat_data *plat_data);
|
||||
void analogix_dp_unbind(struct device *dev, struct device *master, void *data);
|
||||
|
||||
#endif /* _ANALOGIX_DP_H_ */
|
||||
Loading…
Reference in New Issue