clk: rockchip: convert manually created factor clocks to the new type
Clean up the init code and move the creation of factor clocks to the appropriate positions coming from the clock architecture diagrams. This also unifies the artificial separation of the hclk_vcodec etc clocks again. We do keep the separate definition of some watchdog and usb480m pseudo clocks for now, as they're not real factor clocks from the clock-tree but placeholders for fixes to come (usb480m gets supplied by the missing driver for the new usbphy type and the watchdog-gate is sitting somewhere else together which we cannot model currently). Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Heiko Stuebner
parent
29a30c269a
commit
36714529f8
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@ -177,6 +177,8 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
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GATE(0, "gpll_armclk", "gpll", CLK_IGNORE_UNUSED,
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RK2928_CLKGATE_CON(0), 6, GFLAGS),
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FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
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/*
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* Clock-Architecture Diagram 2
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*/
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@ -187,6 +189,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
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RK2928_CLKGATE_CON(0), 8, GFLAGS),
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COMPOSITE_NOGATE(0, "ddrphy2x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
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RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
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FACTOR(0, "ddrphy", "ddrphy2x", 0, 1, 2),
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COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
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RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
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@ -263,6 +266,8 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
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COMPOSITE(0, "aclk_vcodec", mux_pll_src_3plls_p, 0,
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RK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
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RK2928_CLKGATE_CON(3), 11, GFLAGS),
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FACTOR_GATE(HCLK_VCODEC, "hclk_vcodec", "aclk_vcodec", 0, 1, 4,
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RK2928_CLKGATE_CON(3), 12, GFLAGS),
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COMPOSITE(0, "aclk_hvec", mux_pll_src_3plls_p, 0,
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RK2928_CLKSEL_CON(20), 0, 2, MFLAGS, 2, 5, DFLAGS,
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@ -351,6 +356,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
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COMPOSITE_NOMUX(SCLK_MAC, "mac_clk", "mac_clk_ref", 0,
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RK2928_CLKSEL_CON(21), 9, 5, DFLAGS,
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RK2928_CLKGATE_CON(2), 6, GFLAGS),
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FACTOR(0, "sclk_macref_out", "hclk_peri_src", 0, 1, 2),
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MUX(SCLK_HDMI, "dclk_hdmi", mux_dclk_p, 0,
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RK2928_CLKSEL_CON(31), 0, 1, MFLAGS),
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@ -379,8 +385,6 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
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GATE(HCLK_VIO_BUS, "hclk_vio_bus", "hclk_disp_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 12, GFLAGS),
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GATE(HCLK_LCDC, "hclk_lcdc", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
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/* hclk_video gates */
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GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0, RK2928_CLKGATE_CON(3), 12, GFLAGS),
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/* xin24m gates */
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GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK2928_CLKGATE_CON(10), 0, GFLAGS),
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@ -444,34 +448,11 @@ static void __init rk3036_clk_init(struct device_node *np)
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rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
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/* xin12m is created by an cru-internal divider */
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clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
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if (IS_ERR(clk))
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pr_warn("%s: could not register clock xin12m: %ld\n",
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__func__, PTR_ERR(clk));
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clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);
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if (IS_ERR(clk))
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pr_warn("%s: could not register clock usb480m: %ld\n",
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__func__, PTR_ERR(clk));
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clk = clk_register_fixed_factor(NULL, "ddrphy", "ddrphy2x", 0, 1, 2);
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if (IS_ERR(clk))
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pr_warn("%s: could not register clock ddrphy: %ld\n",
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__func__, PTR_ERR(clk));
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clk = clk_register_fixed_factor(NULL, "hclk_vcodec_pre",
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"aclk_vcodec", 0, 1, 4);
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if (IS_ERR(clk))
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pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n",
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__func__, PTR_ERR(clk));
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clk = clk_register_fixed_factor(NULL, "sclk_macref_out",
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"hclk_peri_src", 0, 1, 2);
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if (IS_ERR(clk))
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pr_warn("%s: could not register clock sclk_macref_out: %ld\n",
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__func__, PTR_ERR(clk));
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rockchip_clk_register_plls(rk3036_pll_clks,
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ARRAY_SIZE(rk3036_pll_clks),
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RK3036_GRF_SOC_STATUS0);
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@ -339,6 +339,8 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
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INVERTER(0, "pclk_cif0", "pclkin_cif0",
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RK2928_CLKSEL_CON(30), 8, IFLAGS),
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FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
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/*
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* the 480m are generated inside the usb block from these clocks,
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* but they are also a source for the hsicphy clock.
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@ -754,7 +756,6 @@ static const char *const rk3188_critical_clocks[] __initconst = {
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static void __init rk3188_common_clk_init(struct device_node *np)
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{
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void __iomem *reg_base;
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struct clk *clk;
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reg_base = of_iomap(np, 0);
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if (!reg_base) {
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@ -764,12 +765,6 @@ static void __init rk3188_common_clk_init(struct device_node *np)
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rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
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/* xin12m is created by an cru-internal divider */
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clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
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if (IS_ERR(clk))
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pr_warn("%s: could not register clock xin12m: %ld\n",
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__func__, PTR_ERR(clk));
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rockchip_clk_register_branches(common_clk_branches,
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ARRAY_SIZE(common_clk_branches));
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@ -187,7 +187,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
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RK2928_CLKGATE_CON(7), 1, GFLAGS),
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GATE(0, "ddrc", "ddrphy_pre", CLK_IGNORE_UNUSED,
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RK2928_CLKGATE_CON(8), 5, GFLAGS),
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GATE(0, "ddrphy", "ddrphy_pre", CLK_IGNORE_UNUSED,
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FACTOR_GATE(0, "ddrphy", "ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
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RK2928_CLKGATE_CON(7), 0, GFLAGS),
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/* PD_CORE */
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@ -240,13 +240,13 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
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COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0,
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RK2928_CLKSEL_CON(32), 5, 2, MFLAGS, 0, 5, DFLAGS,
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RK2928_CLKGATE_CON(3), 11, GFLAGS),
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GATE(0, "hclk_vpu_src", "aclk_vpu_pre", 0,
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FACTOR_GATE(0, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1, 4,
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RK2928_CLKGATE_CON(4), 4, GFLAGS),
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COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0,
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RK2928_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS,
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RK2928_CLKGATE_CON(3), 2, GFLAGS),
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GATE(0, "hclk_rkvdec_src", "aclk_rkvdec_pre", 0,
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FACTOR_GATE(0, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1, 4,
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RK2928_CLKGATE_CON(4), 5, GFLAGS),
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COMPOSITE(0, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0,
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@ -371,6 +371,8 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
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MUX(0, "dclk_vop", mux_dclk_vop_p, 0,
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RK2928_CLKSEL_CON(27), 1, 1, MFLAGS),
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FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
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COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0,
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RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, 0, 7, DFLAGS,
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RK2928_CLKGATE_CON(0), 3, GFLAGS),
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@ -624,7 +626,6 @@ static const char *const rk3228_critical_clocks[] __initconst = {
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static void __init rk3228_clk_init(struct device_node *np)
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{
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void __iomem *reg_base;
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struct clk *clk;
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reg_base = of_iomap(np, 0);
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if (!reg_base) {
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@ -634,29 +635,6 @@ static void __init rk3228_clk_init(struct device_node *np)
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rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
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/* xin12m is created by an cru-internal divider */
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clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
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if (IS_ERR(clk))
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pr_warn("%s: could not register clock xin12m: %ld\n",
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__func__, PTR_ERR(clk));
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clk = clk_register_fixed_factor(NULL, "ddrphy_pre", "ddrphy4x", 0, 1, 4);
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if (IS_ERR(clk))
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pr_warn("%s: could not register clock ddrphy_pre: %ld\n",
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__func__, PTR_ERR(clk));
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clk = clk_register_fixed_factor(NULL, "hclk_vpu_pre",
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"hclk_vpu_src", 0, 1, 4);
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if (IS_ERR(clk))
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pr_warn("%s: could not register clock hclk_vpu_pre: %ld\n",
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__func__, PTR_ERR(clk));
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clk = clk_register_fixed_factor(NULL, "hclk_rkvdec_pre",
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"hclk_rkvdec_src", 0, 1, 4);
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if (IS_ERR(clk))
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pr_warn("%s: could not register clock hclk_rkvdec_pre: %ld\n",
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__func__, PTR_ERR(clk));
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rockchip_clk_register_plls(rk3228_pll_clks,
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ARRAY_SIZE(rk3228_pll_clks),
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RK3228_GRF_SOC_STATUS0);
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@ -333,6 +333,8 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
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GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
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RK3288_CLKGATE_CON(0), 7, GFLAGS),
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FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
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COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0,
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RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS,
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RK3288_CLKGATE_CON(4), 1, GFLAGS),
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@ -399,12 +401,10 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
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*/
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GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0,
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RK3288_CLKGATE_CON(9), 0, GFLAGS),
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/*
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* We introduce a virtul node of hclk_vodec_pre_v to split one clock
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* struct with a gate and a fix divider into two node in software.
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*/
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GATE(0, "hclk_vcodec_pre_v", "aclk_vdpu", 0,
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FACTOR_GATE(0, "hclk_vcodec_pre", "aclk_vdpu", 0, 1, 4,
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RK3288_CLKGATE_CON(3), 10, GFLAGS),
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GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
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RK3288_CLKGATE_CON(9), 1, GFLAGS),
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@ -888,18 +888,6 @@ static void __init rk3288_clk_init(struct device_node *np)
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rockchip_clk_init(np, rk3288_cru_base, CLK_NR_CLKS);
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/* xin12m is created by an cru-internal divider */
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clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
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if (IS_ERR(clk))
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pr_warn("%s: could not register clock xin12m: %ld\n",
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__func__, PTR_ERR(clk));
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clk = clk_register_fixed_factor(NULL, "hclk_vcodec_pre",
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"hclk_vcodec_pre_v", 0, 1, 4);
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if (IS_ERR(clk))
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pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n",
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__func__, PTR_ERR(clk));
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/* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */
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clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
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if (IS_ERR(clk))
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@ -248,6 +248,8 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
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* Clock-Architecture Diagram 2
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*/
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FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
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MUX(SCLK_USBPHY480M, "usbphy_480m", mux_usbphy480m_p, CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(13), 8, 1, MFLAGS),
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@ -299,7 +301,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
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COMPOSITE_NOGATE_DIVTBL(0, "ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
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RK3368_CLKSEL_CON(13), 4, 1, MFLAGS, 0, 2, DFLAGS, div_ddrphy_t),
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GATE(0, "sclk_ddr", "ddrphy_div4", CLK_IGNORE_UNUSED,
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FACTOR_GATE(0, "sclk_ddr", "ddrphy_src", CLK_IGNORE_UNUSED, 1, 4,
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RK3368_CLKGATE_CON(6), 14, GFLAGS),
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GATE(0, "sclk_ddr4x", "ddrphy_src", CLK_IGNORE_UNUSED,
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RK3368_CLKGATE_CON(6), 15, GFLAGS),
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@ -392,10 +394,10 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
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RK3368_CLKGATE_CON(4), 7, GFLAGS),
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/*
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* We introduce a virtual node of hclk_vodec_pre_v to split one clock
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* struct with a gate and a fix divider into two node in software.
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* We use aclk_vdpu by default ---GRF_SOC_CON0[7] setting in system,
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* so we ignore the mux and make clocks nodes as following,
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*/
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GATE(0, "hclk_video_pre_v", "aclk_vdpu", 0,
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FACTOR_GATE(0, "hclk_video_pre", "aclk_vdpu", 0, 1, 4,
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RK3368_CLKGATE_CON(4), 8, GFLAGS),
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COMPOSITE(0, "sclk_hevc_cabac_src", mux_pll_src_cpll_gpll_npll_usb_p, 0,
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@ -842,24 +844,6 @@ static void __init rk3368_clk_init(struct device_node *np)
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rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
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/* xin12m is created by a cru-internal divider */
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clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
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if (IS_ERR(clk))
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pr_warn("%s: could not register clock xin12m: %ld\n",
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__func__, PTR_ERR(clk));
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/* ddrphy_div4 is created by a cru-internal divider */
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clk = clk_register_fixed_factor(NULL, "ddrphy_div4", "ddrphy_src", 0, 1, 4);
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if (IS_ERR(clk))
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pr_warn("%s: could not register clock xin12m: %ld\n",
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__func__, PTR_ERR(clk));
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clk = clk_register_fixed_factor(NULL, "hclk_video_pre",
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"hclk_video_pre_v", 0, 1, 4);
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if (IS_ERR(clk))
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pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n",
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__func__, PTR_ERR(clk));
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/* Watchdog pclk is controlled by sgrf_soc_con3[7]. */
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clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
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if (IS_ERR(clk))
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