From 4dcf0f9a6efcfc3763c50f73589da2781ade6f70 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Sun, 15 Oct 2017 11:04:47 +0800 Subject: [PATCH 1/3] arm64: dts: hi3798cv200: add SD card support It adds device mmc@9820000 which is used as SD card on poplar board. Signed-off-by: Shawn Guo Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts | 6 ++++++ arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 12 ++++++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts index a6fd13389f8d..4d5d644abb12 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts @@ -146,6 +146,12 @@ &ir { status = "okay"; }; +&sd0 { + bus-width = <4>; + cap-sd-highspeed; + status = "okay"; +}; + &spi0 { status = "okay"; label = "LS-SPI0"; diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index 75865f8a862a..962bd79139e4 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -192,6 +192,18 @@ spi0: spi@8b1a000 { status = "disabled"; }; + sd0: mmc@9820000 { + compatible = "snps,dw-mshc"; + reg = <0x9820000 0x10000>; + interrupts = ; + clocks = <&crg HISTB_SDIO0_CIU_CLK>, + <&crg HISTB_SDIO0_BIU_CLK>; + clock-names = "ciu", "biu"; + resets = <&crg 0x9c 4>; + reset-names = "reset"; + status = "disabled"; + }; + emmc: mmc@9830000 { compatible = "snps,dw-mshc"; reg = <0x9830000 0x10000>; From e07642fa43434b0eaecdc408aab00b1ef7999000 Mon Sep 17 00:00:00 2001 From: Xu YiPing Date: Thu, 9 Nov 2017 19:18:23 +0800 Subject: [PATCH 2/3] arm64: dts: hi3660: improve pmu description cortex-a73 pmu driver is supported now. hi3660 is 4*a73 + 4*a53, so it should use "cortex-a73-pmu" and "cortex-a53-pmu" instead of "armpmu-v3", then we can use the a73 and a53 events in perf tool directly. Signed-off-by: Xu YiPing Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index ab0b95ba5ae5..723adb107c0d 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -203,21 +203,25 @@ gic: interrupt-controller@e82b0000 { IRQ_TYPE_LEVEL_HIGH)>; }; - pmu { - compatible = "arm,armv8-pmuv3"; + a53-pmu { + compatible = "arm,cortex-a53-pmu"; interrupts = , , , - , - , - , - , - ; + ; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, - <&cpu3>, - <&cpu4>, + <&cpu3>; + }; + + a73-pmu { + compatible = "arm,cortex-a73-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; From 9a9760dede5c71e04b17b2ede594ee7148fd36e2 Mon Sep 17 00:00:00 2001 From: Valentin Schneider Date: Wed, 13 Dec 2017 14:21:06 +0000 Subject: [PATCH 3/3] arm64: dts: hisilicon: Add hi3660 cpu capacity-dmips-mhz information The following dt entries are added: cpus [0-3] (Cortex A53): - capacity-dmips-mhz = <592>; cpus [4-7] (Cortex A73): - capacity-dmips-mhz = <1024>; Those values were obtained by running dhrystone 2.1 on a HiKey960 with the following procedure: - Offline all CPUs but CPU0 (A53) - Set CPU0 frequency to maximum - Run Dhrystone 2.1 for 20 seconds - Offline all CPUs but CPU4 (A73) - set CPU4 frequency to maximum - Run Dhrystone 2.1 for 20 seconds The results are as follows: A53: 129633887 loops A73: 287034147 loops By scaling those values so that the A73s use 1024, we end up with 462 for the A53s. However, they have different maximum frequencies: 1.844GHz for A53s and 2.362GHz for A73s. Thus, we can scale the A53 value to truly represent dmips per MHz, and we end up with 592. The impact of this change can be verified on HiKey960: $ cat /sys/devices/system/cpu/cpu*/cpufreq/scaling_cur_freq 1844000 1844000 1844000 1844000 2362000 2362000 2362000 2362000 $ cat /sys/devices/system/cpu/cpu*/cpu_capacity 462 462 462 462 1024 1024 1024 1024 Signed-off-by: Valentin Schneider Reviewed-by: Leo Yan Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 723adb107c0d..63d4f9dca77f 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -61,6 +61,7 @@ cpu0: cpu@0 { enable-method = "psci"; next-level-cache = <&A53_L2>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <592>; }; cpu1: cpu@1 { @@ -70,6 +71,7 @@ cpu1: cpu@1 { enable-method = "psci"; next-level-cache = <&A53_L2>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <592>; }; cpu2: cpu@2 { @@ -79,6 +81,7 @@ cpu2: cpu@2 { enable-method = "psci"; next-level-cache = <&A53_L2>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <592>; }; cpu3: cpu@3 { @@ -88,6 +91,7 @@ cpu3: cpu@3 { enable-method = "psci"; next-level-cache = <&A53_L2>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <592>; }; cpu4: cpu@100 { @@ -101,6 +105,7 @@ &CPU_NAP &CPU_SLEEP &CLUSTER_SLEEP_1 >; + capacity-dmips-mhz = <1024>; }; cpu5: cpu@101 { @@ -114,6 +119,7 @@ &CPU_NAP &CPU_SLEEP &CLUSTER_SLEEP_1 >; + capacity-dmips-mhz = <1024>; }; cpu6: cpu@102 { @@ -127,6 +133,7 @@ &CPU_NAP &CPU_SLEEP &CLUSTER_SLEEP_1 >; + capacity-dmips-mhz = <1024>; }; cpu7: cpu@103 { @@ -140,6 +147,7 @@ &CPU_NAP &CPU_SLEEP &CLUSTER_SLEEP_1 >; + capacity-dmips-mhz = <1024>; }; idle-states {