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clk: rockchip: add flags for rk3328 dclk_lcdc 

dclk_lcdc can be sourced from a general pll source as well
as the hdmiphy's pll output. We will want to set this source
by hand (to the system-pll-source in most cases) and also
want rate changes to this clock to be able to also touch
the pll source clock if needed, so add CLK_SET_RATE_PARENT
and CLK_SET_RATE_NO_REPARENT for dclk_lcdc.

Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
[ammended commit message]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Zheng Yang 2017-05-25 18:00:24 +08:00 committed by Heiko Stuebner
parent 7f872cb362
commit 36ec03618c
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/rockchip/clk-rk3328.c
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@ -602,7 +602,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
RK3328_CLKGATE_CON(5), 6, GFLAGS), RK3328_CLKGATE_CON(5), 6, GFLAGS),
DIV(DCLK_HDMIPHY, "dclk_hdmiphy", "dclk_lcdc_src", 0, DIV(DCLK_HDMIPHY, "dclk_hdmiphy", "dclk_lcdc_src", 0,
RK3328_CLKSEL_CON(40), 3, 3, DFLAGS), RK3328_CLKSEL_CON(40), 3, 3, DFLAGS),
MUX(DCLK_LCDC, "dclk_lcdc", mux_dclk_lcdc_p, 0, MUX(DCLK_LCDC, "dclk_lcdc", mux_dclk_lcdc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3328_CLKSEL_CON(40), 1, 1, MFLAGS), RK3328_CLKSEL_CON(40), 1, 1, MFLAGS),
/* /*