USB: chipidea updates for v4.3-rc1
The main changes are adding several system interfaces for tuning performance, and each vendors can adjust them according to their design configurations. Others are tiny improvements, like more well siTD supports, USB_DEVICE_A_HNP_SUPPORT supports, etc. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJVzU3lAAoJEEhZKYFQ1nG7nZ4H/AsCAhoiUqcyP4fRziaZzexa F55CuhIVd6vg6vhuiccoUo4XZXR6IsZikczNowWphqXhtQUBr/rvv0VSb2sMxZfn AgdNuinhGUat4rdcf0earr9+EQzjbdrHoxDzFKes21S0vS+J3TaYUk6F7Q6sUL81 t97itMmKBrffMZLsQzB9MJo4E8mD4JNlWu/ezGNu11ZD2/w8Ha7GpyExyb2AGHrs M1rlE6Ph8AKpyECI7OecCxPIDyDRuUQ8Bvj+MkR9BrDX1gOv512ZLfRbIGJCqVOO A2Urzh/jEI9e7ttGqSpMxGYKZ4wvZ7Ta5IvLLseb0vszM2oQGDNHcJx7fKOuUVU= =IIud -----END PGP SIGNATURE----- Merge tag 'usb-ci-v4.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/usb into usb-next Peter writes: USB: chipidea updates for v4.3-rc1 The main changes are adding several system interfaces for tuning performance, and each vendors can adjust them according to their design configurations. Others are tiny improvements, like more well siTD supports, USB_DEVICE_A_HNP_SUPPORT supports, etc.
This commit is contained in:
commit
37a842d36f
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@ -30,6 +30,21 @@ Optional properties:
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argument that indicate usb controller index
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- disable-over-current: (FSL only) disable over current detect
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- external-vbus-divider: (FSL only) enables off-chip resistor divider for Vbus
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- itc-setting: interrupt threshold control register control, the setting
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should be aligned with ITC bits at register USBCMD.
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- ahb-burst-config: it is vendor dependent, the required value should be
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aligned with AHBBRST at SBUSCFG, the range is from 0x0 to 0x7. This
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property is used to change AHB burst configuration, check the chipidea
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spec for meaning of each value. If this property is not existed, it
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will use the reset value.
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- tx-burst-size-dword: it is vendor dependent, the tx burst size in dword
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(4 bytes), This register represents the maximum length of a the burst
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in 32-bit words while moving data from system memory to the USB
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bus, changing this value takes effect only the SBUSCFG.AHBBRST is 0.
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- rx-burst-size-dword: it is vendor dependent, the rx burst size in dword
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(4 bytes), This register represents the maximum length of a the burst
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in 32-bit words while moving data from the USB bus to system memory,
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changing this value takes effect only the SBUSCFG.AHBBRST is 0.
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Example:
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@ -41,4 +56,9 @@ Example:
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phys = <&usb_phy0>;
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phy-names = "usb-phy";
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vbus-supply = <®_usb0_vbus>;
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gadget-itc-setting = <0x4>; /* 4 micro-frames */
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/* Incremental burst of unspecified length */
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ahb-burst-config = <0x0>;
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tx-burst-size-dword = <0x10>; /* 64 bytes */
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rx-burst-size-dword = <0x10>;
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};
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@ -25,6 +25,9 @@
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#define VERSION (0xF << 25)
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#define CIVERSION (0x7 << 29)
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/* SBUSCFG */
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#define AHBBRST_MASK 0x7
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/* HCCPARAMS */
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#define HCCPARAMS_LEN BIT(17)
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@ -53,6 +56,15 @@
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#define DEVICEADDR_USBADRA BIT(24)
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#define DEVICEADDR_USBADR (0x7FUL << 25)
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/* TTCTRL */
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#define TTCTRL_TTHA_MASK (0x7fUL << 24)
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/* Set non-zero value for internal TT Hub address representation */
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#define TTCTRL_TTHA (0x7fUL << 24)
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/* BURSTSIZE */
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#define RX_BURST_MASK 0xff
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#define TX_BURST_MASK 0xff00
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/* PORTSC */
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#define PORTSC_CCS BIT(0)
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#define PORTSC_CSC BIT(1)
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@ -50,6 +50,8 @@ enum ci_hw_regs {
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OP_USBINTR,
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OP_DEVICEADDR,
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OP_ENDPTLISTADDR,
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OP_TTCTRL,
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OP_BURSTSIZE,
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OP_PORTSC,
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OP_DEVLC,
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OP_OTGSC,
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@ -429,4 +431,6 @@ u8 hw_port_test_get(struct ci_hdrc *ci);
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int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
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u32 value, unsigned int timeout_ms);
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void ci_platform_configure(struct ci_hdrc *ci);
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#endif /* __DRIVERS_USB_CHIPIDEA_CI_H */
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@ -29,26 +29,31 @@ struct ci_hdrc_imx_platform_flag {
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};
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static const struct ci_hdrc_imx_platform_flag imx27_usb_data = {
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CI_HDRC_DISABLE_STREAMING,
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};
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static const struct ci_hdrc_imx_platform_flag imx28_usb_data = {
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.flags = CI_HDRC_IMX28_WRITE_FIX |
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CI_HDRC_TURN_VBUS_EARLY_ON,
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CI_HDRC_TURN_VBUS_EARLY_ON |
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CI_HDRC_DISABLE_STREAMING,
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};
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static const struct ci_hdrc_imx_platform_flag imx6q_usb_data = {
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.flags = CI_HDRC_SUPPORTS_RUNTIME_PM |
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CI_HDRC_TURN_VBUS_EARLY_ON,
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CI_HDRC_TURN_VBUS_EARLY_ON |
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CI_HDRC_DISABLE_STREAMING,
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};
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static const struct ci_hdrc_imx_platform_flag imx6sl_usb_data = {
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.flags = CI_HDRC_SUPPORTS_RUNTIME_PM |
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CI_HDRC_TURN_VBUS_EARLY_ON,
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CI_HDRC_TURN_VBUS_EARLY_ON |
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CI_HDRC_DISABLE_HOST_STREAMING,
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};
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static const struct ci_hdrc_imx_platform_flag imx6sx_usb_data = {
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.flags = CI_HDRC_SUPPORTS_RUNTIME_PM |
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CI_HDRC_TURN_VBUS_EARLY_ON,
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CI_HDRC_TURN_VBUS_EARLY_ON |
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CI_HDRC_DISABLE_HOST_STREAMING,
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};
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static const struct of_device_id ci_hdrc_imx_dt_ids[] = {
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@ -104,7 +109,7 @@ static struct imx_usbmisc_data *usbmisc_get_init_data(struct device *dev)
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misc_pdev = of_find_device_by_node(args.np);
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of_node_put(args.np);
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if (!misc_pdev)
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if (!misc_pdev || !platform_get_drvdata(misc_pdev))
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return ERR_PTR(-EPROBE_DEFER);
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data->dev = &misc_pdev->dev;
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@ -126,7 +131,7 @@ static int ci_hdrc_imx_probe(struct platform_device *pdev)
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struct ci_hdrc_platform_data pdata = {
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.name = dev_name(&pdev->dev),
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.capoffset = DEF_CAPOFFSET,
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.flags = CI_HDRC_DISABLE_STREAMING,
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.flags = CI_HDRC_SET_NON_ZERO_TTHA,
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};
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int ret;
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const struct of_device_id *of_id =
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@ -64,6 +64,7 @@
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#include <linux/of.h>
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#include <linux/phy.h>
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#include <linux/regulator/consumer.h>
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#include <linux/usb/ehci_def.h>
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#include "ci.h"
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#include "udc.h"
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@ -84,6 +85,8 @@ static const u8 ci_regs_nolpm[] = {
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[OP_USBINTR] = 0x08U,
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[OP_DEVICEADDR] = 0x14U,
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[OP_ENDPTLISTADDR] = 0x18U,
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[OP_TTCTRL] = 0x1CU,
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[OP_BURSTSIZE] = 0x20U,
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[OP_PORTSC] = 0x44U,
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[OP_DEVLC] = 0x84U,
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[OP_OTGSC] = 0x64U,
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@ -106,6 +109,8 @@ static const u8 ci_regs_lpm[] = {
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[OP_USBINTR] = 0x08U,
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[OP_DEVICEADDR] = 0x14U,
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[OP_ENDPTLISTADDR] = 0x18U,
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[OP_TTCTRL] = 0x1CU,
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[OP_BURSTSIZE] = 0x20U,
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[OP_PORTSC] = 0x44U,
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[OP_DEVLC] = 0x84U,
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[OP_OTGSC] = 0xC4U,
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@ -118,7 +123,7 @@ static const u8 ci_regs_lpm[] = {
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[OP_ENDPTCTRL] = 0xECU,
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};
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static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
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static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
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{
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int i;
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@ -134,7 +139,6 @@ static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
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? ci_regs_lpm[OP_ENDPTCTRL]
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: ci_regs_nolpm[OP_ENDPTCTRL]);
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return 0;
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}
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static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
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@ -403,6 +407,55 @@ static int ci_usb_phy_init(struct ci_hdrc *ci)
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return ret;
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}
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/**
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* ci_platform_configure: do controller configure
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* @ci: the controller
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*
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*/
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void ci_platform_configure(struct ci_hdrc *ci)
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{
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bool is_device_mode, is_host_mode;
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is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC;
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is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC;
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if (is_device_mode &&
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(ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING))
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hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
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if (is_host_mode &&
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(ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING))
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hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
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if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
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if (ci->hw_bank.lpm)
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hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
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else
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hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
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}
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if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA)
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hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);
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hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16);
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if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
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hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
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ci->platdata->ahb_burst_config);
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/* override burst size, take effect only when ahb_burst_config is 0 */
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if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) {
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if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST)
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hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,
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ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
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if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST)
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hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,
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ci->platdata->rx_burst_size);
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}
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}
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/**
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* hw_controller_reset: do controller reset
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* @ci: the controller
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@ -447,16 +500,6 @@ int hw_device_reset(struct ci_hdrc *ci)
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ci->platdata->notify_event(ci,
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CI_HDRC_CONTROLLER_RESET_EVENT);
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if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
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hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
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if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
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if (ci->hw_bank.lpm)
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hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
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else
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hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
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}
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/* USBMODE should be configured step by step */
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hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
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hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
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@ -469,6 +512,8 @@ int hw_device_reset(struct ci_hdrc *ci)
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return -ENODEV;
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}
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ci_platform_configure(ci);
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return 0;
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}
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@ -606,6 +651,50 @@ static int ci_get_platdata(struct device *dev,
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if (of_usb_get_maximum_speed(dev->of_node) == USB_SPEED_FULL)
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platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
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platdata->itc_setting = 1;
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if (of_find_property(dev->of_node, "itc-setting", NULL)) {
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ret = of_property_read_u32(dev->of_node, "itc-setting",
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&platdata->itc_setting);
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if (ret) {
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dev_err(dev,
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"failed to get itc-setting\n");
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return ret;
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}
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}
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if (of_find_property(dev->of_node, "ahb-burst-config", NULL)) {
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ret = of_property_read_u32(dev->of_node, "ahb-burst-config",
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&platdata->ahb_burst_config);
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if (ret) {
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dev_err(dev,
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"failed to get ahb-burst-config\n");
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return ret;
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}
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platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
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}
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if (of_find_property(dev->of_node, "tx-burst-size-dword", NULL)) {
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ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword",
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&platdata->tx_burst_size);
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if (ret) {
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dev_err(dev,
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"failed to get tx-burst-size-dword\n");
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return ret;
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}
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platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST;
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}
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if (of_find_property(dev->of_node, "rx-burst-size-dword", NULL)) {
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ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword",
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&platdata->rx_burst_size);
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if (ret) {
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dev_err(dev,
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"failed to get rx-burst-size-dword\n");
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return ret;
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}
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platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
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}
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return 0;
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}
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|
|
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@ -67,9 +67,11 @@ static int ci_port_test_show(struct seq_file *s, void *data)
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unsigned long flags;
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unsigned mode;
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pm_runtime_get_sync(ci->dev);
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spin_lock_irqsave(&ci->lock, flags);
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mode = hw_port_test_get(ci);
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spin_unlock_irqrestore(&ci->lock, flags);
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pm_runtime_put_sync(ci->dev);
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seq_printf(s, "mode = %u\n", mode);
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|
@ -99,9 +101,11 @@ static ssize_t ci_port_test_write(struct file *file, const char __user *ubuf,
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if (sscanf(buf, "%u", &mode) != 1)
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return -EINVAL;
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|
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pm_runtime_get_sync(ci->dev);
|
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spin_lock_irqsave(&ci->lock, flags);
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ret = hw_port_test_set(ci, mode);
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spin_unlock_irqrestore(&ci->lock, flags);
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pm_runtime_put_sync(ci->dev);
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return ret ? ret : count;
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}
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|
@ -317,8 +321,10 @@ static ssize_t ci_role_write(struct file *file, const char __user *ubuf,
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if (role == CI_ROLE_END || role == ci->role)
|
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return -EINVAL;
|
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pm_runtime_get_sync(ci->dev);
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ci_role_stop(ci);
|
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ret = ci_role_start(ci, role);
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pm_runtime_put_sync(ci->dev);
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return ret ? ret : count;
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}
|
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|
|
|
@ -37,15 +37,14 @@ static int (*orig_bus_suspend)(struct usb_hcd *hcd);
|
|||
|
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struct ehci_ci_priv {
|
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struct regulator *reg_vbus;
|
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struct ci_hdrc *ci;
|
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};
|
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|
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static int ehci_ci_portpower(struct usb_hcd *hcd, int portnum, bool enable)
|
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{
|
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
|
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struct ehci_ci_priv *priv = (struct ehci_ci_priv *)ehci->priv;
|
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struct ci_hdrc *ci = priv->ci;
|
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struct device *dev = hcd->self.controller;
|
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struct ci_hdrc *ci = dev_get_drvdata(dev);
|
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int ret = 0;
|
||||
int port = HCS_N_PORTS(ehci->hcs_params);
|
||||
|
||||
|
@ -78,9 +77,25 @@ static int ehci_ci_portpower(struct usb_hcd *hcd, int portnum, bool enable)
|
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return 0;
|
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};
|
||||
|
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static int ehci_ci_reset(struct usb_hcd *hcd)
|
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{
|
||||
struct device *dev = hcd->self.controller;
|
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struct ci_hdrc *ci = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
ret = ehci_setup(hcd);
|
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if (ret)
|
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return ret;
|
||||
|
||||
ci_platform_configure(ci);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct ehci_driver_overrides ehci_ci_overrides = {
|
||||
.extra_priv_size = sizeof(struct ehci_ci_priv),
|
||||
.port_power = ehci_ci_portpower,
|
||||
.reset = ehci_ci_reset,
|
||||
};
|
||||
|
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static irqreturn_t host_irq(struct ci_hdrc *ci)
|
||||
|
@ -123,7 +138,6 @@ static int host_start(struct ci_hdrc *ci)
|
|||
|
||||
priv = (struct ehci_ci_priv *)ehci->priv;
|
||||
priv->reg_vbus = NULL;
|
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priv->ci = ci;
|
||||
|
||||
if (ci->platdata->reg_vbus && !ci_otg_is_fsm_mode(ci)) {
|
||||
if (ci->platdata->flags & CI_HDRC_TURN_VBUS_EARLY_ON) {
|
||||
|
@ -153,12 +167,6 @@ static int host_start(struct ci_hdrc *ci)
|
|||
}
|
||||
}
|
||||
|
||||
if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
|
||||
hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
|
||||
|
||||
if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED)
|
||||
hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
|
||||
|
||||
return ret;
|
||||
|
||||
disable_reg:
|
||||
|
|
|
@ -525,7 +525,6 @@ static int ci_otg_start_host(struct otg_fsm *fsm, int on)
|
|||
ci_role_start(ci, CI_ROLE_HOST);
|
||||
} else {
|
||||
ci_role_stop(ci);
|
||||
hw_device_reset(ci);
|
||||
ci_role_start(ci, CI_ROLE_GADGET);
|
||||
}
|
||||
return 0;
|
||||
|
|
|
@ -445,7 +445,7 @@ static int _hardware_enqueue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
|
|||
rest -= count;
|
||||
}
|
||||
|
||||
if (hwreq->req.zero && hwreq->req.length
|
||||
if (hwreq->req.zero && hwreq->req.length && hwep->dir == TX
|
||||
&& (hwreq->req.length % hwep->ep.maxpacket == 0))
|
||||
add_td_to_list(hwep, hwreq, 0);
|
||||
|
||||
|
@ -1090,6 +1090,13 @@ __acquires(ci->lock)
|
|||
if (ci_otg_is_fsm_mode(ci))
|
||||
err = otg_a_alt_hnp_support(ci);
|
||||
break;
|
||||
case USB_DEVICE_A_HNP_SUPPORT:
|
||||
if (ci_otg_is_fsm_mode(ci)) {
|
||||
ci->gadget.a_hnp_support = 1;
|
||||
err = isr_setup_status_phase(
|
||||
ci);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
goto delegate;
|
||||
}
|
||||
|
|
|
@ -54,6 +54,7 @@
|
|||
#define MX53_USB_PHYCTRL1_PLLDIV_MASK 0x3
|
||||
#define MX53_USB_PLL_DIV_24_MHZ 0x01
|
||||
|
||||
#define MX6_BM_NON_BURST_SETTING BIT(1)
|
||||
#define MX6_BM_OVER_CUR_DIS BIT(7)
|
||||
#define MX6_BM_WAKEUP_ENABLE BIT(10)
|
||||
#define MX6_BM_ID_WAKEUP BIT(16)
|
||||
|
@ -255,14 +256,21 @@ static int usbmisc_imx6q_init(struct imx_usbmisc_data *data)
|
|||
if (data->index > 3)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&usbmisc->lock, flags);
|
||||
|
||||
if (data->disable_oc) {
|
||||
spin_lock_irqsave(&usbmisc->lock, flags);
|
||||
reg = readl(usbmisc->base + data->index * 4);
|
||||
writel(reg | MX6_BM_OVER_CUR_DIS,
|
||||
usbmisc->base + data->index * 4);
|
||||
spin_unlock_irqrestore(&usbmisc->lock, flags);
|
||||
}
|
||||
|
||||
/* SoC non-burst setting */
|
||||
reg = readl(usbmisc->base + data->index * 4);
|
||||
writel(reg | MX6_BM_NON_BURST_SETTING,
|
||||
usbmisc->base + data->index * 4);
|
||||
|
||||
spin_unlock_irqrestore(&usbmisc->lock, flags);
|
||||
|
||||
usbmisc_imx6q_set_wakeup(data, false);
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -19,8 +19,11 @@ struct ci_hdrc_platform_data {
|
|||
enum usb_phy_interface phy_mode;
|
||||
unsigned long flags;
|
||||
#define CI_HDRC_REGS_SHARED BIT(0)
|
||||
#define CI_HDRC_DISABLE_DEVICE_STREAMING BIT(1)
|
||||
#define CI_HDRC_SUPPORTS_RUNTIME_PM BIT(2)
|
||||
#define CI_HDRC_DISABLE_STREAMING BIT(3)
|
||||
#define CI_HDRC_DISABLE_HOST_STREAMING BIT(3)
|
||||
#define CI_HDRC_DISABLE_STREAMING (CI_HDRC_DISABLE_DEVICE_STREAMING | \
|
||||
CI_HDRC_DISABLE_HOST_STREAMING)
|
||||
/*
|
||||
* Only set it when DCCPARAMS.DC==1 and DCCPARAMS.HC==1,
|
||||
* but otg is not supported (no register otgsc).
|
||||
|
@ -29,6 +32,10 @@ struct ci_hdrc_platform_data {
|
|||
#define CI_HDRC_IMX28_WRITE_FIX BIT(5)
|
||||
#define CI_HDRC_FORCE_FULLSPEED BIT(6)
|
||||
#define CI_HDRC_TURN_VBUS_EARLY_ON BIT(7)
|
||||
#define CI_HDRC_SET_NON_ZERO_TTHA BIT(8)
|
||||
#define CI_HDRC_OVERRIDE_AHB_BURST BIT(9)
|
||||
#define CI_HDRC_OVERRIDE_TX_BURST BIT(10)
|
||||
#define CI_HDRC_OVERRIDE_RX_BURST BIT(11)
|
||||
enum usb_dr_mode dr_mode;
|
||||
#define CI_HDRC_CONTROLLER_RESET_EVENT 0
|
||||
#define CI_HDRC_CONTROLLER_STOPPED_EVENT 1
|
||||
|
@ -36,6 +43,11 @@ struct ci_hdrc_platform_data {
|
|||
struct regulator *reg_vbus;
|
||||
struct usb_otg_caps ci_otg_caps;
|
||||
bool tpl_support;
|
||||
/* interrupt threshold setting */
|
||||
u32 itc_setting;
|
||||
u32 ahb_burst_config;
|
||||
u32 tx_burst_size;
|
||||
u32 rx_burst_size;
|
||||
};
|
||||
|
||||
/* Default offset of capability registers */
|
||||
|
|
Loading…
Reference in New Issue