Altera TSE: Work around unaligned DMA receive packet issue with Altera SGDMA
This patch works around a recently discovered unaligned receive dma problem with the Altera SGMDA. The Altera SGDMA component cannot be configured to DMA data to unaligned addresses for receive packet operations from the Triple Speed Ethernet component because of a potential data transfer corruption that can occur. This patch addresses this issue by utilizing the shift 16 bits feature of the Altera Triple Speed Ethernet component and modifying the receive buffer physical addresses accordingly such that the target receive DMA address is always aligned on a 32-bit boundary. Signed-off-by: Vince Bridgers <vbridgers2013@gmail.com> Tested-by: Matthew Gerlach <mgerlach@altera.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Vince Bridgers
David S. Miller
parent
c2163260ea
commit
37c0ffaad2
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@ -29,6 +29,10 @@ void msgdma_uninitialize(struct altera_tse_private *priv)
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{
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}
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void msgdma_start_rxdma(struct altera_tse_private *priv)
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{
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}
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void msgdma_reset(struct altera_tse_private *priv)
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{
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int counter;
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@ -154,7 +158,7 @@ u32 msgdma_tx_completions(struct altera_tse_private *priv)
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/* Put buffer to the mSGDMA RX FIFO
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*/
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int msgdma_add_rx_desc(struct altera_tse_private *priv,
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void msgdma_add_rx_desc(struct altera_tse_private *priv,
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struct tse_buffer *rxbuffer)
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{
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struct msgdma_extended_desc *desc = priv->rx_dma_desc;
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@ -175,7 +179,6 @@ int msgdma_add_rx_desc(struct altera_tse_private *priv,
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iowrite32(0, &desc->burst_seq_num);
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iowrite32(0x00010001, &desc->stride);
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iowrite32(control, &desc->control);
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return 1;
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}
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/* status is returned on upper 16 bits,
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@ -25,10 +25,11 @@ void msgdma_disable_txirq(struct altera_tse_private *);
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void msgdma_clear_rxirq(struct altera_tse_private *);
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void msgdma_clear_txirq(struct altera_tse_private *);
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u32 msgdma_tx_completions(struct altera_tse_private *);
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int msgdma_add_rx_desc(struct altera_tse_private *, struct tse_buffer *);
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void msgdma_add_rx_desc(struct altera_tse_private *, struct tse_buffer *);
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int msgdma_tx_buffer(struct altera_tse_private *, struct tse_buffer *);
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u32 msgdma_rx_status(struct altera_tse_private *);
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int msgdma_initialize(struct altera_tse_private *);
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void msgdma_uninitialize(struct altera_tse_private *);
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void msgdma_start_rxdma(struct altera_tse_private *);
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#endif /* __ALTERA_MSGDMA_H__ */
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@ -64,11 +64,15 @@ queue_rx_peekhead(struct altera_tse_private *priv);
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int sgdma_initialize(struct altera_tse_private *priv)
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{
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priv->txctrlreg = SGDMA_CTRLREG_ILASTD;
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priv->txctrlreg = SGDMA_CTRLREG_ILASTD |
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SGDMA_CTRLREG_INTEN;
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priv->rxctrlreg = SGDMA_CTRLREG_IDESCRIP |
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SGDMA_CTRLREG_INTEN |
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SGDMA_CTRLREG_ILASTD;
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priv->sgdmadesclen = sizeof(sgdma_descrip);
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INIT_LIST_HEAD(&priv->txlisthd);
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INIT_LIST_HEAD(&priv->rxlisthd);
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@ -93,6 +97,16 @@ int sgdma_initialize(struct altera_tse_private *priv)
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return -EINVAL;
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}
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/* Initialize descriptor memory to all 0's, sync memory to cache */
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memset(priv->tx_dma_desc, 0, priv->txdescmem);
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memset(priv->rx_dma_desc, 0, priv->rxdescmem);
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dma_sync_single_for_device(priv->device, priv->txdescphys,
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priv->txdescmem, DMA_TO_DEVICE);
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dma_sync_single_for_device(priv->device, priv->rxdescphys,
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priv->rxdescmem, DMA_TO_DEVICE);
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return 0;
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}
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@ -130,26 +144,23 @@ void sgdma_reset(struct altera_tse_private *priv)
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iowrite32(0, &prxsgdma->control);
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}
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/* For SGDMA, interrupts remain enabled after initially enabling,
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* so no need to provide implementations for abstract enable
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* and disable
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*/
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void sgdma_enable_rxirq(struct altera_tse_private *priv)
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{
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struct sgdma_csr *csr = (struct sgdma_csr *)priv->rx_dma_csr;
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priv->rxctrlreg |= SGDMA_CTRLREG_INTEN;
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tse_set_bit(&csr->control, SGDMA_CTRLREG_INTEN);
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}
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void sgdma_enable_txirq(struct altera_tse_private *priv)
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{
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struct sgdma_csr *csr = (struct sgdma_csr *)priv->tx_dma_csr;
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priv->txctrlreg |= SGDMA_CTRLREG_INTEN;
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tse_set_bit(&csr->control, SGDMA_CTRLREG_INTEN);
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}
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/* for SGDMA, RX interrupts remain enabled after enabling */
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void sgdma_disable_rxirq(struct altera_tse_private *priv)
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{
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}
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/* for SGDMA, TX interrupts remain enabled after enabling */
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void sgdma_disable_txirq(struct altera_tse_private *priv)
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{
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}
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@ -219,11 +230,15 @@ u32 sgdma_tx_completions(struct altera_tse_private *priv)
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return ready;
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}
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int sgdma_add_rx_desc(struct altera_tse_private *priv,
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struct tse_buffer *rxbuffer)
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void sgdma_start_rxdma(struct altera_tse_private *priv)
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{
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sgdma_async_read(priv);
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}
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void sgdma_add_rx_desc(struct altera_tse_private *priv,
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struct tse_buffer *rxbuffer)
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{
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queue_rx(priv, rxbuffer);
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return sgdma_async_read(priv);
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}
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/* status is returned on upper 16 bits,
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@ -240,28 +255,52 @@ u32 sgdma_rx_status(struct altera_tse_private *priv)
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unsigned int pktstatus = 0;
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struct tse_buffer *rxbuffer = NULL;
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dma_sync_single_for_cpu(priv->device,
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priv->rxdescphys,
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priv->rxdescmem,
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DMA_BIDIRECTIONAL);
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u32 sts = ioread32(&csr->status);
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desc = &base[0];
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if ((ioread32(&csr->status) & SGDMA_STSREG_EOP) ||
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(desc->status & SGDMA_STATUS_EOP)) {
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if (sts & SGDMA_STSREG_EOP) {
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dma_sync_single_for_cpu(priv->device,
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priv->rxdescphys,
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priv->sgdmadesclen,
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DMA_FROM_DEVICE);
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pktlength = desc->bytes_xferred;
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pktstatus = desc->status & 0x3f;
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rxstatus = pktstatus;
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rxstatus = rxstatus << 16;
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rxstatus |= (pktlength & 0xffff);
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desc->status = 0;
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if (rxstatus) {
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desc->status = 0;
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rxbuffer = dequeue_rx(priv);
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if (rxbuffer == NULL)
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rxbuffer = dequeue_rx(priv);
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if (rxbuffer == NULL)
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netdev_info(priv->dev,
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"sgdma rx and rx queue empty!\n");
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/* Clear control */
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iowrite32(0, &csr->control);
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/* clear status */
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iowrite32(0xf, &csr->status);
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/* kick the rx sgdma after reaping this descriptor */
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pktsrx = sgdma_async_read(priv);
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} else {
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/* If the SGDMA indicated an end of packet on recv,
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* then it's expected that the rxstatus from the
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* descriptor is non-zero - meaning a valid packet
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* with a nonzero length, or an error has been
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* indicated. if not, then all we can do is signal
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* an error and return no packet received. Most likely
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* there is a system design error, or an error in the
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* underlying kernel (cache or cache management problem)
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*/
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netdev_err(priv->dev,
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"sgdma rx and rx queue empty!\n");
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/* kick the rx sgdma after reaping this descriptor */
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"SGDMA RX Error Info: %x, %x, %x\n",
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sts, desc->status, rxstatus);
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}
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} else if (sts == 0) {
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pktsrx = sgdma_async_read(priv);
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}
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@ -319,13 +358,14 @@ static int sgdma_async_read(struct altera_tse_private *priv)
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struct sgdma_descrip *cdesc = &descbase[0];
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struct sgdma_descrip *ndesc = &descbase[1];
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unsigned int sts = ioread32(&csr->status);
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struct tse_buffer *rxbuffer = NULL;
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if (!sgdma_rxbusy(priv)) {
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rxbuffer = queue_rx_peekhead(priv);
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if (rxbuffer == NULL)
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if (rxbuffer == NULL) {
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netdev_err(priv->dev, "no rx buffers available\n");
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return 0;
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}
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sgdma_descrip(cdesc, /* current descriptor */
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ndesc, /* next descriptor */
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@ -337,17 +377,10 @@ static int sgdma_async_read(struct altera_tse_private *priv)
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0, /* read fixed: NA for rx dma */
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0); /* SOP: NA for rx DMA */
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/* clear control and status */
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iowrite32(0, &csr->control);
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/* If status available, clear those bits */
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if (sts & 0xf)
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iowrite32(0xf, &csr->status);
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dma_sync_single_for_device(priv->device,
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priv->rxdescphys,
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priv->rxdescmem,
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DMA_BIDIRECTIONAL);
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priv->sgdmadesclen,
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DMA_TO_DEVICE);
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iowrite32(lower_32_bits(sgdma_rxphysaddr(priv, cdesc)),
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&csr->next_descrip);
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@ -374,7 +407,7 @@ static int sgdma_async_write(struct altera_tse_private *priv,
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iowrite32(0x1f, &csr->status);
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dma_sync_single_for_device(priv->device, priv->txdescphys,
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priv->txdescmem, DMA_TO_DEVICE);
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priv->sgdmadesclen, DMA_TO_DEVICE);
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iowrite32(lower_32_bits(sgdma_txphysaddr(priv, desc)),
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&csr->next_descrip);
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@ -26,10 +26,11 @@ void sgdma_clear_rxirq(struct altera_tse_private *);
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void sgdma_clear_txirq(struct altera_tse_private *);
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int sgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *);
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u32 sgdma_tx_completions(struct altera_tse_private *);
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int sgdma_add_rx_desc(struct altera_tse_private *priv, struct tse_buffer *);
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void sgdma_add_rx_desc(struct altera_tse_private *priv, struct tse_buffer *);
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void sgdma_status(struct altera_tse_private *);
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u32 sgdma_rx_status(struct altera_tse_private *);
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int sgdma_initialize(struct altera_tse_private *);
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void sgdma_uninitialize(struct altera_tse_private *);
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void sgdma_start_rxdma(struct altera_tse_private *);
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#endif /* __ALTERA_SGDMA_H__ */
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@ -390,10 +390,11 @@ struct altera_dmaops {
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void (*clear_rxirq)(struct altera_tse_private *);
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int (*tx_buffer)(struct altera_tse_private *, struct tse_buffer *);
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u32 (*tx_completions)(struct altera_tse_private *);
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int (*add_rx_desc)(struct altera_tse_private *, struct tse_buffer *);
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void (*add_rx_desc)(struct altera_tse_private *, struct tse_buffer *);
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u32 (*get_rx_status)(struct altera_tse_private *);
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int (*init_dma)(struct altera_tse_private *);
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void (*uninit_dma)(struct altera_tse_private *);
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void (*start_rxdma)(struct altera_tse_private *);
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};
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/* This structure is private to each device.
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@ -453,6 +454,7 @@ struct altera_tse_private {
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u32 rxctrlreg;
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dma_addr_t rxdescphys;
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dma_addr_t txdescphys;
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size_t sgdmadesclen;
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struct list_head txlisthd;
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struct list_head rxlisthd;
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@ -224,6 +224,7 @@ static int tse_init_rx_buffer(struct altera_tse_private *priv,
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dev_kfree_skb_any(rxbuffer->skb);
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return -EINVAL;
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}
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rxbuffer->dma_addr &= (dma_addr_t)~3;
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rxbuffer->len = len;
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return 0;
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}
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@ -425,9 +426,10 @@ static int tse_rx(struct altera_tse_private *priv, int limit)
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priv->dev->stats.rx_bytes += pktlength;
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entry = next_entry;
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tse_rx_refill(priv);
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}
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tse_rx_refill(priv);
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return count;
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}
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@ -520,7 +522,6 @@ static irqreturn_t altera_isr(int irq, void *dev_id)
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struct altera_tse_private *priv;
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unsigned long int flags;
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if (unlikely(!dev)) {
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pr_err("%s: invalid dev pointer\n", __func__);
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return IRQ_NONE;
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@ -868,13 +869,13 @@ static int init_mac(struct altera_tse_private *priv)
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/* Disable RX/TX shift 16 for alignment of all received frames on 16-bit
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* start address
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*/
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tse_clear_bit(&mac->rx_cmd_stat, ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16);
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tse_set_bit(&mac->rx_cmd_stat, ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16);
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tse_clear_bit(&mac->tx_cmd_stat, ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 |
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ALTERA_TSE_TX_CMD_STAT_OMIT_CRC);
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/* Set the MAC options */
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cmd = ioread32(&mac->command_config);
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cmd |= MAC_CMDCFG_PAD_EN; /* Padding Removal on Receive */
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cmd &= ~MAC_CMDCFG_PAD_EN; /* No padding Removal on Receive */
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cmd &= ~MAC_CMDCFG_CRC_FWD; /* CRC Removal */
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cmd |= MAC_CMDCFG_RX_ERR_DISC; /* Automatically discard frames
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* with CRC errors
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@ -882,6 +883,12 @@ static int init_mac(struct altera_tse_private *priv)
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cmd |= MAC_CMDCFG_CNTL_FRM_ENA;
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cmd &= ~MAC_CMDCFG_TX_ENA;
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cmd &= ~MAC_CMDCFG_RX_ENA;
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/* Default speed and duplex setting, full/100 */
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cmd &= ~MAC_CMDCFG_HD_ENA;
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cmd &= ~MAC_CMDCFG_ETH_SPEED;
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cmd &= ~MAC_CMDCFG_ENA_10;
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iowrite32(cmd, &mac->command_config);
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if (netif_msg_hw(priv))
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@ -1085,17 +1092,19 @@ static int tse_open(struct net_device *dev)
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spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
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/* Start MAC Rx/Tx */
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spin_lock(&priv->mac_cfg_lock);
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tse_set_mac(priv, true);
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spin_unlock(&priv->mac_cfg_lock);
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if (priv->phydev)
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phy_start(priv->phydev);
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napi_enable(&priv->napi);
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netif_start_queue(dev);
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priv->dmaops->start_rxdma(priv);
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/* Start MAC Rx/Tx */
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spin_lock(&priv->mac_cfg_lock);
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tse_set_mac(priv, true);
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spin_unlock(&priv->mac_cfg_lock);
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return 0;
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tx_request_irq_error:
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@ -1167,7 +1176,6 @@ static struct net_device_ops altera_tse_netdev_ops = {
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.ndo_validate_addr = eth_validate_addr,
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};
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static int request_and_map(struct platform_device *pdev, const char *name,
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struct resource **res, void __iomem **ptr)
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{
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@ -1496,6 +1504,7 @@ struct altera_dmaops altera_dtype_sgdma = {
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.get_rx_status = sgdma_rx_status,
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.init_dma = sgdma_initialize,
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.uninit_dma = sgdma_uninitialize,
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.start_rxdma = sgdma_start_rxdma,
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};
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struct altera_dmaops altera_dtype_msgdma = {
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@ -1514,6 +1523,7 @@ struct altera_dmaops altera_dtype_msgdma = {
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.get_rx_status = msgdma_rx_status,
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.init_dma = msgdma_initialize,
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.uninit_dma = msgdma_uninitialize,
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.start_rxdma = msgdma_start_rxdma,
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};
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static struct of_device_id altera_tse_ids[] = {
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