clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI
On R-Car V3M (AKA R8A77970), the SD0CKCR is laid out differently than on the other R-Car gen3 SoCs. In fact, the layout is the same as on R-Car gen2 SoCs, so we'll need to copy the divisor tables from the R-Car gen2 driver. We'll also need to support the SoC specific clock types, thus we're adding CLK_TYPE_GEN3_SOC_BASE at the end of 'enum rcar_gen3_clk_types', declare SD0H/SDH clocks in 'enum r8a77970_clk_types', and handle those clocks in the overridden cpg_clk_register() method; then, finally, add the SD-IF module clock (derived from the SD0 clock). Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Sergei Shtylyov
Geert Uytterhoeven
parent
0a87bf6cd5
commit
381081ffc2
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@ -1,7 +1,7 @@
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/*
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* r8a77970 Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2017 Cogent Embedded Inc.
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* Copyright (C) 2017-2018 Cogent Embedded Inc.
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*
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* Based on r8a7795-cpg-mssr.c
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*
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@ -12,6 +12,7 @@
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* the Free Software Foundation; version 2 of the License.
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*/
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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@ -22,6 +23,13 @@
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#include "renesas-cpg-mssr.h"
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#include "rcar-gen3-cpg.h"
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#define CPG_SD0CKCR 0x0074
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enum r8a77970_clk_types {
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CLK_TYPE_R8A77970_SD0H = CLK_TYPE_GEN3_SOC_BASE,
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CLK_TYPE_R8A77970_SD0,
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};
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R8A77970_CLK_OSC,
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@ -42,6 +50,20 @@ enum clk_ids {
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MOD_CLK_BASE
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};
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static spinlock_t cpg_lock;
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static const struct clk_div_table cpg_sd0h_div_table[] = {
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{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
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{ 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
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{ 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
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};
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static const struct clk_div_table cpg_sd0_div_table[] = {
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{ 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
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{ 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
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{ 0, 0 },
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};
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static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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@ -68,6 +90,10 @@ static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
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DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_PLL1_DIV2, 12, 1),
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DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_PLL1_DIV2, 24, 1),
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DEF_BASE("sd0h", R8A77970_CLK_SD0H, CLK_TYPE_R8A77970_SD0H,
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CLK_PLL1_DIV2),
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DEF_BASE("sd0", R8A77970_CLK_SD0, CLK_TYPE_R8A77970_SD0, CLK_PLL1_DIV2),
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DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
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DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
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@ -92,6 +118,7 @@ static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = {
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DEF_MOD("mfis", 213, R8A77970_CLK_S2D2),
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DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1),
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DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1),
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DEF_MOD("sd-if", 314, R8A77970_CLK_SD0),
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DEF_MOD("rwdt", 402, R8A77970_CLK_R),
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DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
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DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1),
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@ -173,11 +200,46 @@ static int __init r8a77970_cpg_mssr_init(struct device *dev)
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if (error)
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return error;
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spin_lock_init(&cpg_lock);
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cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
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return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
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}
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static struct clk * __init r8a77970_cpg_clk_register(struct device *dev,
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const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
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struct clk **clks, void __iomem *base,
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struct raw_notifier_head *notifiers)
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{
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const struct clk_div_table *table;
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const struct clk *parent;
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unsigned int shift;
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switch (core->type) {
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case CLK_TYPE_R8A77970_SD0H:
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table = cpg_sd0h_div_table;
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shift = 8;
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break;
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case CLK_TYPE_R8A77970_SD0:
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table = cpg_sd0_div_table;
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shift = 4;
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break;
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default:
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return rcar_gen3_cpg_clk_register(dev, core, info, clks, base,
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notifiers);
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}
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parent = clks[core->parent];
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if (IS_ERR(parent))
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return ERR_CAST(parent);
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return clk_register_divider_table(NULL, core->name,
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__clk_get_name(parent), 0,
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base + CPG_SD0CKCR,
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shift, 4, 0, table, &cpg_lock);
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}
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const struct cpg_mssr_info r8a77970_cpg_mssr_info __initconst = {
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/* Core Clocks */
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.core_clks = r8a77970_core_clks,
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@ -196,5 +258,5 @@ const struct cpg_mssr_info r8a77970_cpg_mssr_info __initconst = {
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/* Callbacks */
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.init = r8a77970_cpg_mssr_init,
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.cpg_clk_register = rcar_gen3_cpg_clk_register,
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.cpg_clk_register = r8a77970_cpg_clk_register,
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};
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@ -25,6 +25,9 @@ enum rcar_gen3_clk_types {
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CLK_TYPE_GEN3_Z2,
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CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
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CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
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/* SoC specific definitions start here */
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CLK_TYPE_GEN3_SOC_BASE,
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};
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#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
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