x86/AMD: Fix last level cache topology for AMD Fam17h systems
On AMD Fam17h systems, the last level cache is not resident in the northbridge. Therefore, we cannot assign cpu_llc_id to the same value as Node ID as we have been doing until now. We should rather look at the ApicID bits of the core to provide us the last level cache ID info. Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Andy Lutomirski <luto@kernel.org> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Huang Rui <ray.huang@amd.com> Cc: Ingo Molnar <mingo@kernel.org> Cc: Jacob Shin <jacob.w.shin@gmail.com> Link: http://lkml.kernel.org/r/1446582899-9378-1-git-send-email-Aravind.Gopalakrishnan@amd.com Signed-off-by: Borislav Petkov <bp@suse.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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@ -352,6 +352,7 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c)
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#ifdef CONFIG_SMP
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#ifdef CONFIG_SMP
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unsigned bits;
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unsigned bits;
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int cpu = smp_processor_id();
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int cpu = smp_processor_id();
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unsigned int socket_id, core_complex_id;
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bits = c->x86_coreid_bits;
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bits = c->x86_coreid_bits;
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/* Low order bits define the core id (index of core in socket) */
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/* Low order bits define the core id (index of core in socket) */
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@ -361,6 +362,18 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c)
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/* use socket ID also for last level cache */
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/* use socket ID also for last level cache */
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per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
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per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
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amd_get_topology(c);
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amd_get_topology(c);
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/*
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* Fix percpu cpu_llc_id here as LLC topology is different
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* for Fam17h systems.
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*/
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if (c->x86 != 0x17 || !cpuid_edx(0x80000006))
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return;
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socket_id = (c->apicid >> bits) - 1;
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core_complex_id = (c->apicid & ((1 << bits) - 1)) >> 3;
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per_cpu(cpu_llc_id, cpu) = (socket_id << 3) | core_complex_id;
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#endif
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#endif
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}
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}
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