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drm/amd/display: fix issue related to infopacket was not transmitted 

Check in code was incorrect, and infopacket is only transmitted after update
function is called multiple times.
Purpose of the function was to check if infopackets are being enabled, and
then enable global control. Fix the code to do this.

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Anthony Koo 2018-04-11 13:19:56 -04:00 committed by Alex Deucher
parent 3d777c82bd
commit 388277b170
2 changed files with 13 additions and 23 deletions
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25
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
View File

@ -819,7 +819,7 @@ static void dce110_stream_encoder_update_dp_info_packets(
const struct encoder_info_frame *info_frame) const struct encoder_info_frame *info_frame)
{ {
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
uint32_t value = REG_READ(DP_SEC_CNTL); uint32_t value = 0;
if (info_frame->vsc.valid) if (info_frame->vsc.valid)
dce110_update_generic_info_packet( dce110_update_generic_info_packet(
@ -853,6 +853,7 @@ static void dce110_stream_encoder_update_dp_info_packets(
* Therefore we need to enable master bit * Therefore we need to enable master bit
* if at least on of the fields is not 0 * if at least on of the fields is not 0
*/ */
value = REG_READ(DP_SEC_CNTL);
if (value) if (value)
REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
} }
@ -862,7 +863,7 @@ static void dce110_stream_encoder_stop_dp_info_packets(
{ {
/* stop generic packets on DP */ /* stop generic packets on DP */
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
uint32_t value = REG_READ(DP_SEC_CNTL); uint32_t value = 0;
if (enc110->se_mask->DP_SEC_AVI_ENABLE) { if (enc110->se_mask->DP_SEC_AVI_ENABLE) {
REG_SET_7(DP_SEC_CNTL, 0, REG_SET_7(DP_SEC_CNTL, 0,
@ -875,25 +876,10 @@ static void dce110_stream_encoder_stop_dp_info_packets(
DP_SEC_STREAM_ENABLE, 0); DP_SEC_STREAM_ENABLE, 0);
} }
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
if (enc110->se_mask->DP_SEC_GSP7_ENABLE) {
REG_SET_10(DP_SEC_CNTL, 0,
DP_SEC_GSP0_ENABLE, 0,
DP_SEC_GSP1_ENABLE, 0,
DP_SEC_GSP2_ENABLE, 0,
DP_SEC_GSP3_ENABLE, 0,
DP_SEC_GSP4_ENABLE, 0,
DP_SEC_GSP5_ENABLE, 0,
DP_SEC_GSP6_ENABLE, 0,
DP_SEC_GSP7_ENABLE, 0,
DP_SEC_MPG_ENABLE, 0,
DP_SEC_STREAM_ENABLE, 0);
}
#endif
/* this register shared with audio info frame. /* this register shared with audio info frame.
* therefore we need to keep master enabled * therefore we need to keep master enabled
* if at least one of the fields is not 0 */ * if at least one of the fields is not 0 */
value = REG_READ(DP_SEC_CNTL);
if (value) if (value)
REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
@ -1496,7 +1482,7 @@ static void dce110_se_disable_dp_audio(
struct stream_encoder *enc) struct stream_encoder *enc)
{ {
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
uint32_t value = REG_READ(DP_SEC_CNTL); uint32_t value = 0;
/* Disable Audio packets */ /* Disable Audio packets */
REG_UPDATE_5(DP_SEC_CNTL, REG_UPDATE_5(DP_SEC_CNTL,
@ -1508,6 +1494,7 @@ static void dce110_se_disable_dp_audio(
/* This register shared with encoder info frame. Therefore we need to /* This register shared with encoder info frame. Therefore we need to
keep master enabled if at least on of the fields is not 0 */ keep master enabled if at least on of the fields is not 0 */
value = REG_READ(DP_SEC_CNTL);
if (value != 0) if (value != 0)
REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);

11
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
View File

@ -686,7 +686,7 @@ void enc1_stream_encoder_update_dp_info_packets(
const struct encoder_info_frame *info_frame) const struct encoder_info_frame *info_frame)
{ {
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
uint32_t value = REG_READ(DP_SEC_CNTL); uint32_t value = 0;
if (info_frame->vsc.valid) if (info_frame->vsc.valid)
enc1_update_generic_info_packet( enc1_update_generic_info_packet(
@ -713,6 +713,7 @@ void enc1_stream_encoder_update_dp_info_packets(
REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
/* This bit is the master enable bit. /* This bit is the master enable bit.
* When enabling secondary stream engine, * When enabling secondary stream engine,
* this master bit must also be set. * this master bit must also be set.
@ -720,6 +721,7 @@ void enc1_stream_encoder_update_dp_info_packets(
* Therefore we need to enable master bit * Therefore we need to enable master bit
* if at least on of the fields is not 0 * if at least on of the fields is not 0
*/ */
value = REG_READ(DP_SEC_CNTL);
if (value) if (value)
REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
} }
@ -729,7 +731,7 @@ void enc1_stream_encoder_stop_dp_info_packets(
{ {
/* stop generic packets on DP */ /* stop generic packets on DP */
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
uint32_t value = REG_READ(DP_SEC_CNTL); uint32_t value = 0;
REG_SET_10(DP_SEC_CNTL, 0, REG_SET_10(DP_SEC_CNTL, 0,
DP_SEC_GSP0_ENABLE, 0, DP_SEC_GSP0_ENABLE, 0,
@ -746,7 +748,7 @@ void enc1_stream_encoder_stop_dp_info_packets(
/* this register shared with audio info frame. /* this register shared with audio info frame.
* therefore we need to keep master enabled * therefore we need to keep master enabled
* if at least one of the fields is not 0 */ * if at least one of the fields is not 0 */
value = REG_READ(DP_SEC_CNTL);
if (value) if (value)
REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
@ -1356,7 +1358,7 @@ static void enc1_se_disable_dp_audio(
struct stream_encoder *enc) struct stream_encoder *enc)
{ {
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
uint32_t value = REG_READ(DP_SEC_CNTL); uint32_t value = 0;
/* Disable Audio packets */ /* Disable Audio packets */
REG_UPDATE_5(DP_SEC_CNTL, REG_UPDATE_5(DP_SEC_CNTL,
@ -1369,6 +1371,7 @@ static void enc1_se_disable_dp_audio(
/* This register shared with encoder info frame. Therefore we need to /* This register shared with encoder info frame. Therefore we need to
* keep master enabled if at least on of the fields is not 0 * keep master enabled if at least on of the fields is not 0
*/ */
value = REG_READ(DP_SEC_CNTL);
if (value != 0) if (value != 0)
REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);