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drm/i915/bxt: add WaDisableMaskBasedCammingInRCC workaround 

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ben Widawsky 2015-03-11 10:54:53 +02:00 committed by Daniel Vetter
parent 868434c51e
commit 38a39a7be7
2 changed files with 13 additions and 0 deletions
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4
drivers/gpu/drm/i915/i915_reg.h
View File

@ -5346,6 +5346,10 @@ enum skl_disp_power_wells {
#define HDC_FORCE_NON_COHERENT (1<<4)
#define HDC_BARRIER_PERFORMANCE_DISABLE (1<<10)
/* GEN9 chicken */
#define SLICE_ECO_CHICKEN0 0x7308
#define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
/* WaCatErrorRejectionIssue */
#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)

9
drivers/gpu/drm/i915/intel_ringbuffer.c
View File

@ -966,6 +966,15 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
GEN9_CCS_TLB_PREFETCH_ENABLE);
/*
* FIXME: don't apply the following on BXT for stepping C. On BXT A0
* the flag reads back as 0.
*/
/* WaDisableMaskBasedCammingInRCC:bxtA */
if (IS_BROXTON(dev))
WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
PIXEL_MASK_CAMMING_DISABLE);
return 0;
}