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x86/apic: Invoke perf_events_lapic_init() after enabling APIC 

If the APIC is soft disabled then unmasking an LVT entry does not work and
the write is ignored. perf_events_lapic_init() tries to do so.

Move the invocation after the point where the APIC has been enabled.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20190722105218.962517234@linutronix.de
This commit is contained in:
Thomas Gleixner 2019-07-22 20:47:07 +02:00
parent 2591bc4e8d
commit 39c89dff9c
1 changed files with 2 additions and 3 deletions
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5
arch/x86/kernel/apic/apic.c
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@ -1517,7 +1517,6 @@ static void setup_local_APIC(void)
int logical_apicid, ldr_apicid; int logical_apicid, ldr_apicid;
#endif #endif
if (disable_apic) { if (disable_apic) {
disable_ioapic_support(); disable_ioapic_support();
return; return;
@ -1532,8 +1531,6 @@ static void setup_local_APIC(void)
apic_write(APIC_ESR, 0); apic_write(APIC_ESR, 0);
} }
#endif #endif
perf_events_lapic_init();
/* /*
* Double-check whether this APIC is really registered. * Double-check whether this APIC is really registered.
* This is meaningless in clustered apic mode, so we skip it. * This is meaningless in clustered apic mode, so we skip it.
@ -1617,6 +1614,8 @@ static void setup_local_APIC(void)
value |= SPURIOUS_APIC_VECTOR; value |= SPURIOUS_APIC_VECTOR;
apic_write(APIC_SPIV, value); apic_write(APIC_SPIV, value);
perf_events_lapic_init();
/* /*
* Set up LVT0, LVT1: * Set up LVT0, LVT1:
* *