remoteproc: qcom: Introduce Hexagon V5 based WCSS driver
IPQ8074 has an integrated Hexagon dsp core q6v5 and a wireless lan (Lithium) IP. An mdt type single image format is used for the firmware. So the mdt_load function can be directly used to load the firmware. Also add the relevant resets required for this core. Acked-by: Rob Herring <robh@kernel.org> (bindings) Signed-off-by: Sricharan R <sricharan@codeaurora.org> [bjorn: Rewrote as a separate driver, intead of extending q6v5_pil.c] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Sricharan R
Bjorn Andersson
parent
7d674731f3
commit
3a3d4163e0
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@ -8,6 +8,7 @@ on the Qualcomm Hexagon core.
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Value type: <string>
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Definition: must be one of:
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"qcom,q6v5-pil",
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"qcom,ipq8074-wcss-pil"
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"qcom,msm8916-mss-pil",
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"qcom,msm8974-mss-pil"
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"qcom,msm8996-mss-pil"
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@ -50,11 +51,15 @@ on the Qualcomm Hexagon core.
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Usage: required
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Value type: <phandle>
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Definition: reference to the reset-controller for the modem sub-system
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reference to the list of 3 reset-controllers for the
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wcss sub-system
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- reset-names:
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Usage: required
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Value type: <stringlist>
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Definition: must be "mss_restart"
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Definition: must be "mss_restart" for the modem sub-system
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Definition: must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
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for the wcss syb-system
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- cx-supply:
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- mss-supply:
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@ -123,6 +123,21 @@ config QCOM_Q6V5_PIL
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Say y here to support the Qualcomm Peripherial Image Loader for the
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Hexagon V5 based remote processors.
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config QCOM_Q6V5_WCSS
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tristate "Qualcomm Hexagon based WCSS Peripheral Image Loader"
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depends on OF && ARCH_QCOM
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depends on QCOM_SMEM
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depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
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depends on QCOM_SYSMON || QCOM_SYSMON=n
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select MFD_SYSCON
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select QCOM_MDT_LOADER
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select QCOM_Q6V5_COMMON
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select QCOM_RPROC_COMMON
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select QCOM_SCM
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help
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Say y here to support the Qualcomm Peripheral Image Loader for the
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Hexagon V5 based WCSS remote processors.
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config QCOM_SYSMON
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tristate "Qualcomm sysmon driver"
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depends on RPMSG
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@ -18,6 +18,7 @@ obj-$(CONFIG_QCOM_ADSP_PIL) += qcom_adsp_pil.o
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obj-$(CONFIG_QCOM_RPROC_COMMON) += qcom_common.o
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obj-$(CONFIG_QCOM_Q6V5_COMMON) += qcom_q6v5.o
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obj-$(CONFIG_QCOM_Q6V5_PIL) += qcom_q6v5_pil.o
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obj-$(CONFIG_QCOM_Q6V5_WCSS) += qcom_q6v5_wcss.o
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obj-$(CONFIG_QCOM_SYSMON) += qcom_sysmon.o
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obj-$(CONFIG_QCOM_WCNSS_PIL) += qcom_wcnss_pil.o
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qcom_wcnss_pil-y += qcom_wcnss.o
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@ -0,0 +1,601 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2018 Linaro Ltd.
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* Copyright (C) 2014 Sony Mobile Communications AB
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* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
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*/
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_reserved_mem.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <linux/soc/qcom/mdt_loader.h>
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#include "qcom_common.h"
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#include "qcom_q6v5.h"
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#define WCSS_CRASH_REASON 421
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/* Q6SS Register Offsets */
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#define Q6SS_RESET_REG 0x014
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#define Q6SS_GFMUX_CTL_REG 0x020
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#define Q6SS_PWR_CTL_REG 0x030
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#define Q6SS_MEM_PWR_CTL 0x0B0
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/* AXI Halt Register Offsets */
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#define AXI_HALTREQ_REG 0x0
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#define AXI_HALTACK_REG 0x4
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#define AXI_IDLE_REG 0x8
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#define HALT_ACK_TIMEOUT_MS 100
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/* Q6SS_RESET */
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#define Q6SS_STOP_CORE BIT(0)
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#define Q6SS_CORE_ARES BIT(1)
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#define Q6SS_BUS_ARES_ENABLE BIT(2)
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/* Q6SS_GFMUX_CTL */
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#define Q6SS_CLK_ENABLE BIT(1)
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/* Q6SS_PWR_CTL */
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#define Q6SS_L2DATA_STBY_N BIT(18)
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#define Q6SS_SLP_RET_N BIT(19)
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#define Q6SS_CLAMP_IO BIT(20)
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#define QDSS_BHS_ON BIT(21)
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/* Q6SS parameters */
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#define Q6SS_LDO_BYP BIT(25)
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#define Q6SS_BHS_ON BIT(24)
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#define Q6SS_CLAMP_WL BIT(21)
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#define Q6SS_CLAMP_QMC_MEM BIT(22)
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#define HALT_CHECK_MAX_LOOPS 200
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#define Q6SS_XO_CBCR GENMASK(5, 3)
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/* Q6SS config/status registers */
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#define TCSR_GLOBAL_CFG0 0x0
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#define TCSR_GLOBAL_CFG1 0x4
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#define SSCAON_CONFIG 0x8
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#define SSCAON_STATUS 0xc
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#define Q6SS_BHS_STATUS 0x78
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#define Q6SS_RST_EVB 0x10
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#define BHS_EN_REST_ACK BIT(0)
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#define SSCAON_ENABLE BIT(13)
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#define SSCAON_BUS_EN BIT(15)
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#define SSCAON_BUS_MUX_MASK GENMASK(18, 16)
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#define MEM_BANKS 19
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#define TCSR_WCSS_CLK_MASK 0x1F
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#define TCSR_WCSS_CLK_ENABLE 0x14
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struct q6v5_wcss {
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struct device *dev;
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void __iomem *reg_base;
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void __iomem *rmb_base;
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struct regmap *halt_map;
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u32 halt_q6;
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u32 halt_wcss;
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u32 halt_nc;
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struct reset_control *wcss_aon_reset;
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struct reset_control *wcss_reset;
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struct reset_control *wcss_q6_reset;
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struct qcom_q6v5 q6v5;
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phys_addr_t mem_phys;
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phys_addr_t mem_reloc;
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void *mem_region;
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size_t mem_size;
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};
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static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
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{
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int ret;
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u32 val;
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int i;
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/* Assert resets, stop core */
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val = readl(wcss->reg_base + Q6SS_RESET_REG);
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val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
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writel(val, wcss->reg_base + Q6SS_RESET_REG);
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/* BHS require xo cbcr to be enabled */
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val = readl(wcss->reg_base + Q6SS_XO_CBCR);
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val |= 0x1;
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writel(val, wcss->reg_base + Q6SS_XO_CBCR);
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/* Read CLKOFF bit to go low indicating CLK is enabled */
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ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR,
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val, !(val & BIT(31)), 1,
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HALT_CHECK_MAX_LOOPS);
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if (ret) {
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dev_err(wcss->dev,
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"xo cbcr enabling timed out (rc:%d)\n", ret);
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return ret;
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}
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/* Enable power block headswitch and wait for it to stabilize */
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val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
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val |= Q6SS_BHS_ON;
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writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
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udelay(1);
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/* Put LDO in bypass mode */
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val |= Q6SS_LDO_BYP;
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writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
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/* Deassert Q6 compiler memory clamp */
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val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
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val &= ~Q6SS_CLAMP_QMC_MEM;
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writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
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/* Deassert memory peripheral sleep and L2 memory standby */
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val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
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writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
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/* Turn on L1, L2, ETB and JU memories 1 at a time */
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val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);
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for (i = MEM_BANKS; i >= 0; i--) {
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val |= BIT(i);
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writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL);
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/*
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* Read back value to ensure the write is done then
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* wait for 1us for both memory peripheral and data
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* array to turn on.
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*/
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val |= readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);
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udelay(1);
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}
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/* Remove word line clamp */
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val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
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val &= ~Q6SS_CLAMP_WL;
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writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
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/* Remove IO clamp */
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val &= ~Q6SS_CLAMP_IO;
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writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
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/* Bring core out of reset */
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val = readl(wcss->reg_base + Q6SS_RESET_REG);
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val &= ~Q6SS_CORE_ARES;
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writel(val, wcss->reg_base + Q6SS_RESET_REG);
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/* Turn on core clock */
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val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
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val |= Q6SS_CLK_ENABLE;
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writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
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/* Start core execution */
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val = readl(wcss->reg_base + Q6SS_RESET_REG);
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val &= ~Q6SS_STOP_CORE;
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writel(val, wcss->reg_base + Q6SS_RESET_REG);
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return 0;
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}
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static int q6v5_wcss_start(struct rproc *rproc)
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{
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struct q6v5_wcss *wcss = rproc->priv;
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int ret;
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qcom_q6v5_prepare(&wcss->q6v5);
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/* Release Q6 and WCSS reset */
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ret = reset_control_deassert(wcss->wcss_reset);
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if (ret) {
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dev_err(wcss->dev, "wcss_reset failed\n");
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return ret;
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}
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ret = reset_control_deassert(wcss->wcss_q6_reset);
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if (ret) {
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dev_err(wcss->dev, "wcss_q6_reset failed\n");
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goto wcss_reset;
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}
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/* Lithium configuration - clock gating and bus arbitration */
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ret = regmap_update_bits(wcss->halt_map,
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wcss->halt_nc + TCSR_GLOBAL_CFG0,
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TCSR_WCSS_CLK_MASK,
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TCSR_WCSS_CLK_ENABLE);
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if (ret)
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goto wcss_q6_reset;
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ret = regmap_update_bits(wcss->halt_map,
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wcss->halt_nc + TCSR_GLOBAL_CFG1,
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1, 0);
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if (ret)
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goto wcss_q6_reset;
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/* Write bootaddr to EVB so that Q6WCSS will jump there after reset */
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writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB);
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ret = q6v5_wcss_reset(wcss);
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if (ret)
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goto wcss_q6_reset;
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ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ);
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if (ret == -ETIMEDOUT)
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dev_err(wcss->dev, "start timed out\n");
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return ret;
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wcss_q6_reset:
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reset_control_assert(wcss->wcss_q6_reset);
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wcss_reset:
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reset_control_assert(wcss->wcss_reset);
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return ret;
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}
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static void q6v5_wcss_halt_axi_port(struct q6v5_wcss *wcss,
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struct regmap *halt_map,
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u32 offset)
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{
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unsigned long timeout;
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unsigned int val;
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int ret;
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/* Check if we're already idle */
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ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
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if (!ret && val)
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return;
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/* Assert halt request */
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regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);
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/* Wait for halt */
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timeout = jiffies + msecs_to_jiffies(HALT_ACK_TIMEOUT_MS);
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for (;;) {
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ret = regmap_read(halt_map, offset + AXI_HALTACK_REG, &val);
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if (ret || val || time_after(jiffies, timeout))
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break;
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msleep(1);
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}
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ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
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if (ret || !val)
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dev_err(wcss->dev, "port failed halt\n");
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/* Clear halt request (port will remain halted until reset) */
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regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
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}
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static int q6v5_wcss_powerdown(struct q6v5_wcss *wcss)
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{
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int ret;
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u32 val;
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/* 1 - Assert WCSS/Q6 HALTREQ */
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q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_wcss);
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/* 2 - Enable WCSSAON_CONFIG */
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val = readl(wcss->rmb_base + SSCAON_CONFIG);
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val |= SSCAON_ENABLE;
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writel(val, wcss->rmb_base + SSCAON_CONFIG);
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/* 3 - Set SSCAON_CONFIG */
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val |= SSCAON_BUS_EN;
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val &= ~SSCAON_BUS_MUX_MASK;
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writel(val, wcss->rmb_base + SSCAON_CONFIG);
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/* 4 - SSCAON_CONFIG 1 */
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val |= BIT(1);
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writel(val, wcss->rmb_base + SSCAON_CONFIG);
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/* 5 - wait for SSCAON_STATUS */
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ret = readl_poll_timeout(wcss->rmb_base + SSCAON_STATUS,
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val, (val & 0xffff) == 0x400, 1000,
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HALT_CHECK_MAX_LOOPS);
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if (ret) {
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dev_err(wcss->dev,
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"can't get SSCAON_STATUS rc:%d)\n", ret);
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return ret;
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}
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/* 6 - De-assert WCSS_AON reset */
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reset_control_assert(wcss->wcss_aon_reset);
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/* 7 - Disable WCSSAON_CONFIG 13 */
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val = readl(wcss->rmb_base + SSCAON_CONFIG);
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val &= ~SSCAON_ENABLE;
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writel(val, wcss->rmb_base + SSCAON_CONFIG);
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/* 8 - De-assert WCSS/Q6 HALTREQ */
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reset_control_assert(wcss->wcss_reset);
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return 0;
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}
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static int q6v5_q6_powerdown(struct q6v5_wcss *wcss)
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{
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int ret;
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u32 val;
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int i;
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/* 1 - Halt Q6 bus interface */
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q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_q6);
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/* 2 - Disable Q6 Core clock */
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val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
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val &= ~Q6SS_CLK_ENABLE;
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writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
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/* 3 - Clamp I/O */
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val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
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val |= Q6SS_CLAMP_IO;
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writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
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/* 4 - Clamp WL */
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val |= QDSS_BHS_ON;
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writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
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/* 5 - Clear Erase standby */
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val &= ~Q6SS_L2DATA_STBY_N;
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writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
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/* 6 - Clear Sleep RTN */
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val &= ~Q6SS_SLP_RET_N;
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writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
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/* 7 - turn off Q6 memory foot/head switch one bank at a time */
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for (i = 0; i < 20; i++) {
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val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);
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val &= ~BIT(i);
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writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL);
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mdelay(1);
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}
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/* 8 - Assert QMC memory RTN */
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val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
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val |= Q6SS_CLAMP_QMC_MEM;
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writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
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/* 9 - Turn off BHS */
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val &= ~Q6SS_BHS_ON;
|
||||
writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
|
||||
udelay(1);
|
||||
|
||||
/* 10 - Wait till BHS Reset is done */
|
||||
ret = readl_poll_timeout(wcss->reg_base + Q6SS_BHS_STATUS,
|
||||
val, !(val & BHS_EN_REST_ACK), 1000,
|
||||
HALT_CHECK_MAX_LOOPS);
|
||||
if (ret) {
|
||||
dev_err(wcss->dev, "BHS_STATUS not OFF (rc:%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* 11 - Assert WCSS reset */
|
||||
reset_control_assert(wcss->wcss_reset);
|
||||
|
||||
/* 12 - Assert Q6 reset */
|
||||
reset_control_assert(wcss->wcss_q6_reset);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int q6v5_wcss_stop(struct rproc *rproc)
|
||||
{
|
||||
struct q6v5_wcss *wcss = rproc->priv;
|
||||
int ret;
|
||||
|
||||
/* WCSS powerdown */
|
||||
ret = qcom_q6v5_request_stop(&wcss->q6v5);
|
||||
if (ret == -ETIMEDOUT) {
|
||||
dev_err(wcss->dev, "timed out on wait\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = q6v5_wcss_powerdown(wcss);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Q6 Power down */
|
||||
ret = q6v5_q6_powerdown(wcss);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
qcom_q6v5_unprepare(&wcss->q6v5);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void *q6v5_wcss_da_to_va(struct rproc *rproc, u64 da, int len)
|
||||
{
|
||||
struct q6v5_wcss *wcss = rproc->priv;
|
||||
int offset;
|
||||
|
||||
offset = da - wcss->mem_reloc;
|
||||
if (offset < 0 || offset + len > wcss->mem_size)
|
||||
return NULL;
|
||||
|
||||
return wcss->mem_region + offset;
|
||||
}
|
||||
|
||||
static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw)
|
||||
{
|
||||
struct q6v5_wcss *wcss = rproc->priv;
|
||||
|
||||
return qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware,
|
||||
0, wcss->mem_region, wcss->mem_phys,
|
||||
wcss->mem_size, &wcss->mem_reloc);
|
||||
}
|
||||
|
||||
static const struct rproc_ops q6v5_wcss_ops = {
|
||||
.start = q6v5_wcss_start,
|
||||
.stop = q6v5_wcss_stop,
|
||||
.da_to_va = q6v5_wcss_da_to_va,
|
||||
.load = q6v5_wcss_load,
|
||||
.get_boot_addr = rproc_elf_get_boot_addr,
|
||||
};
|
||||
|
||||
static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss)
|
||||
{
|
||||
struct device *dev = wcss->dev;
|
||||
|
||||
wcss->wcss_aon_reset = devm_reset_control_get(dev, "wcss_aon_reset");
|
||||
if (IS_ERR(wcss->wcss_aon_reset)) {
|
||||
dev_err(wcss->dev, "unable to acquire wcss_aon_reset\n");
|
||||
return PTR_ERR(wcss->wcss_aon_reset);
|
||||
}
|
||||
|
||||
wcss->wcss_reset = devm_reset_control_get(dev, "wcss_reset");
|
||||
if (IS_ERR(wcss->wcss_reset)) {
|
||||
dev_err(wcss->dev, "unable to acquire wcss_reset\n");
|
||||
return PTR_ERR(wcss->wcss_reset);
|
||||
}
|
||||
|
||||
wcss->wcss_q6_reset = devm_reset_control_get(dev, "wcss_q6_reset");
|
||||
if (IS_ERR(wcss->wcss_q6_reset)) {
|
||||
dev_err(wcss->dev, "unable to acquire wcss_q6_reset\n");
|
||||
return PTR_ERR(wcss->wcss_q6_reset);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int q6v5_wcss_init_mmio(struct q6v5_wcss *wcss,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
struct of_phandle_args args;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
|
||||
wcss->reg_base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(wcss->reg_base))
|
||||
return PTR_ERR(wcss->reg_base);
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
|
||||
wcss->rmb_base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(wcss->rmb_base))
|
||||
return PTR_ERR(wcss->rmb_base);
|
||||
|
||||
ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
|
||||
"qcom,halt-regs", 3, 0, &args);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
wcss->halt_map = syscon_node_to_regmap(args.np);
|
||||
of_node_put(args.np);
|
||||
if (IS_ERR(wcss->halt_map))
|
||||
return PTR_ERR(wcss->halt_map);
|
||||
|
||||
wcss->halt_q6 = args.args[0];
|
||||
wcss->halt_wcss = args.args[1];
|
||||
wcss->halt_nc = args.args[2];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss)
|
||||
{
|
||||
struct reserved_mem *rmem = NULL;
|
||||
struct device_node *node;
|
||||
struct device *dev = wcss->dev;
|
||||
|
||||
node = of_parse_phandle(dev->of_node, "memory-region", 0);
|
||||
if (node)
|
||||
rmem = of_reserved_mem_lookup(node);
|
||||
of_node_put(node);
|
||||
|
||||
if (!rmem) {
|
||||
dev_err(dev, "unable to acquire memory-region\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
wcss->mem_phys = rmem->base;
|
||||
wcss->mem_reloc = rmem->base;
|
||||
wcss->mem_size = rmem->size;
|
||||
wcss->mem_region = devm_ioremap_wc(dev, wcss->mem_phys, wcss->mem_size);
|
||||
if (!wcss->mem_region) {
|
||||
dev_err(dev, "unable to map memory region: %pa+%pa\n",
|
||||
&rmem->base, &rmem->size);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int q6v5_wcss_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct q6v5_wcss *wcss;
|
||||
struct rproc *rproc;
|
||||
int ret;
|
||||
|
||||
rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_wcss_ops,
|
||||
"IPQ8074/q6_fw.mdt", sizeof(*wcss));
|
||||
if (!rproc) {
|
||||
dev_err(&pdev->dev, "failed to allocate rproc\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
wcss = rproc->priv;
|
||||
wcss->dev = &pdev->dev;
|
||||
|
||||
ret = q6v5_wcss_init_mmio(wcss, pdev);
|
||||
if (ret)
|
||||
goto free_rproc;
|
||||
|
||||
ret = q6v5_alloc_memory_region(wcss);
|
||||
if (ret)
|
||||
goto free_rproc;
|
||||
|
||||
ret = q6v5_wcss_init_reset(wcss);
|
||||
if (ret)
|
||||
goto free_rproc;
|
||||
|
||||
ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, WCSS_CRASH_REASON, NULL);
|
||||
if (ret)
|
||||
goto free_rproc;
|
||||
|
||||
ret = rproc_add(rproc);
|
||||
if (ret)
|
||||
goto free_rproc;
|
||||
|
||||
platform_set_drvdata(pdev, rproc);
|
||||
|
||||
return 0;
|
||||
|
||||
free_rproc:
|
||||
rproc_free(rproc);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int q6v5_wcss_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct rproc *rproc = platform_get_drvdata(pdev);
|
||||
|
||||
rproc_del(rproc);
|
||||
rproc_free(rproc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id q6v5_wcss_of_match[] = {
|
||||
{ .compatible = "qcom,ipq8074-wcss-pil" },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, q6v5_wcss_of_match);
|
||||
|
||||
static struct platform_driver q6v5_wcss_driver = {
|
||||
.probe = q6v5_wcss_probe,
|
||||
.remove = q6v5_wcss_remove,
|
||||
.driver = {
|
||||
.name = "qcom-q6v5-wcss-pil",
|
||||
.of_match_table = q6v5_wcss_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(q6v5_wcss_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Hexagon WCSS Peripheral Image Loader");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue