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Renesas ARM DT updates for v5.18 

- External interrupt (INTC-EX) support for the R-Car V3U SoC,
   - Initial support for the RZ/G2LC and RZ/V2L SoCs, and the RZ/G2LC and
     RZ/V2L SMARC EVK development boards,
   - Support for MAX9286 GMSL deserializers and GSML cameras on the Eagle
     and Condor development boards,
   - NAND support for the RZ/N1D SoC,
   - DMA engine (SYS-DMAC) support for the R-Car S4-8 SoC,
   - LVDS support for the R-Car M3-W+ SoC,
   - HDMI output and 9-axis sensor support for the Kingfisher (ULCB
     extension) board,
   - MAX96712 GMSL serializer support for the Falcon development board,
   - MOST network support for the R-Car H3, M3-W, M3-W+, M3-N, E3, and D3
     SoCs,
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-arm-dt-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM DT updates for v5.18

  - External interrupt (INTC-EX) support for the R-Car V3U SoC,
  - Initial support for the RZ/G2LC and RZ/V2L SoCs, and the RZ/G2LC and
    RZ/V2L SMARC EVK development boards,
  - Support for MAX9286 GMSL deserializers and GSML cameras on the Eagle
    and Condor development boards,
  - NAND support for the RZ/N1D SoC,
  - DMA engine (SYS-DMAC) support for the R-Car S4-8 SoC,
  - LVDS support for the R-Car M3-W+ SoC,
  - HDMI output and 9-axis sensor support for the Kingfisher (ULCB
    extension) board,
  - MAX96712 GMSL serializer support for the Falcon development board,
  - MOST network support for the R-Car H3, M3-W, M3-W+, M3-N, E3, and D3
    SoCs,
  - Miscellaneous fixes and improvements.

* tag 'renesas-arm-dt-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (27 commits)
  arm64: dts: renesas: rzg2lc-smarc: Use SW_SD0_DEV_SEL macro for eMMC/SDHI device selection
  arm64: dts: renesas: rzg2lc-smarc: Enable CANFD channel 1
  arm64: dts: renesas: rzg2lc-smarc: Enable SCIF1 on carrier board
  arm64: dts: renesas: rzg2lc-smarc: Add macros for DIP-Switch settings
  arm64: dts: renesas: rzg2l-smarc: Add common dtsi file
  arm64: dts: renesas: rzg2lc-smarc: Enable microSD on SMARC platform
  arm64: dts: renesas: rzg2lc-smarc-som: Enable eMMC on SMARC platform
  arm64: dts: renesas: Add initial device tree for RZ/V2L SMARC EVK
  arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC
  dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions
  arm64: dts: renesas: ulcb/ulcb-kf: switch to use audio-graph-card2 for sound
  arm64: dts: renesas: rcar-gen3: Add MOST devices
  arm64: dts: renesas: Miscellaneous whitespace fixes
  arm64: dts: renesas: falcon-csi-dsi: Add and connect MAX96712
  arm64: dts: renesas: ulcb-kf: Add 9-asix sensor device
  arm64: dts: renesas: ulcb-kf: Add KF HDMI output
  arm64: dts: renesas: r8a77961: Add lvds0 device node
  arm64: dts: renesas: r8a779f0: Add sys-dmac nodes
  ARM: dts: r9a06g032: Describe the NAND controller
  arm64: dts: renesas: Add GMSL cameras .dtsi
  ...

Link: https://lore.kernel.org/r/cover.1644587200.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-02-25 15:23:11 +01:00
parent 4d9b86eb38 5c65ad1278
commit 3b34d3a919
40 changed files with 2905 additions and 418 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
arch/arm/boot/dts/r9a06g032.dtsi
View File

@ -173,6 +173,17 @@ pinctrl: pinctrl@40067000 {
status = "okay";
};
nand_controller: nand-controller@40102000 {
compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc";
reg = <0x40102000 0x2000>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>;
clock-names = "hclk", "eclk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gic: interrupt-controller@44101000 {
compatible = "arm,gic-400", "arm,cortex-a7-gic";
interrupt-controller;

3
arch/arm64/boot/dts/renesas/Makefile
View File

@ -75,4 +75,7 @@ dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb

9
arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
View File

@ -359,11 +359,10 @@ versaclock6_bb: clock-controller@6a {
clocks = <&x304_clk>;
clock-names = "xin";
assigned-clocks = <&versaclock6_bb 1>,
<&versaclock6_bb 2>,
<&versaclock6_bb 3>,
<&versaclock6_bb 4>;
assigned-clock-rates = <24000000>, <24000000>, <24000000>, <24576000>;
assigned-clocks = <&versaclock6_bb 1>, <&versaclock6_bb 2>,
<&versaclock6_bb 3>, <&versaclock6_bb 4>;
assigned-clock-rates = <24000000>, <24000000>, <24000000>,
<24576000>;
OUT1 {
idt,mode = <VC5_CMOS>;

1
arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi
View File

@ -293,7 +293,6 @@ &sdhi2 {
vqmmc-supply = <&reg_1p8v>;
non-removable;
cap-power-off-card;
pm-ignore-notify;
keep-power-in-suspend;
mmc-pwrseq = <&wlan_pwrseq>;
status = "okay";

332
arch/arm64/boot/dts/renesas/gmsl-cameras.dtsi Normal file
View File

@ -0,0 +1,332 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Ideas on Board <kieran.bingham@ideasonboard.com>
* Copyright (C) 2021 Jacopo Mondi <jacopo+renesas@jmondi.org>
*
* Device Tree Source (overlay) that describes GMSL camera connected to
* Fakra connectors for the Eagle V3M and Condor V3H (and compatible) boards.
*
* The following cameras are currently supported: RDACM20 and RDACM21.
*
* The board .dts file that include this has to select which cameras are in use
* by specifying the camera model with:
*
* #define GMSL_CAMERA_RDACM20
* or
* #define GMSL_CAMERA_RDACM21
*
* And which cameras are connected to the board by defining:
* for GMSL channel 0:
* #define GMSL_CAMERA_0
* #define GMSL_CAMERA_1
* #define GMSL_CAMERA_2
* #define GMSL_CAMERA_3
*
* for GMSL channel 1:
* #define GMSL_CAMERA_4
* #define GMSL_CAMERA_5
* #define GMSL_CAMERA_6
* #define GMSL_CAMERA_7
*/
#include <dt-bindings/gpio/gpio.h>
/* Validate the board file settings. */
#if !defined(GMSL_CAMERA_RDACM20) && !defined(GMSL_CAMERA_RDACM21)
#error "Camera model should be defined by the board file"
#endif
#if defined(GMSL_CAMERA_RDACM20) && defined(GMSL_CAMERA_RDACM21)
#error "A single camera model should be selected"
#endif
#if !defined(GMSL_CAMERA_0) && !defined(GMSL_CAMERA_1) && \
!defined(GMSL_CAMERA_2) && !defined(GMSL_CAMERA_3) && \
!defined(GMSL_CAMERA_4) && !defined(GMSL_CAMERA_5) && \
!defined(GMSL_CAMERA_6) && !defined(GMSL_CAMERA_7)
#error "At least one camera should be selected"
#endif
/* Deduce from the enabled cameras which GMSL channels are active. */
#if defined(GMSL_CAMERA_0) || defined(GMSL_CAMERA_1) || \
defined(GMSL_CAMERA_2) || defined(GMSL_CAMERA_3)
#define GMSL_0
#endif
#if defined(GMSL_CAMERA_4) || defined(GMSL_CAMERA_5) || \
defined(GMSL_CAMERA_6) || defined(GMSL_CAMERA_7)
#define GMSL_1
#endif
/* Deduce the camera model compatible string. */
#if defined(GMSL_CAMERA_RDACM20)
#define GMSL_CAMERA_MODEL "imi,rdacm20"
#elif defined(GMSL_CAMERA_RDACM21)
#define GMSL_CAMERA_MODEL "imi,rdacm21"
#endif
#ifdef GMSL_0
&vin0 {
status = "okay";
};
&vin1 {
status = "okay";
};
&vin2 {
status = "okay";
};
&vin3 {
status = "okay";
};
&gmsl0 {
status = "okay";
#if defined(GMSL_CAMERA_RDACM21)
maxim,reverse-channel-microvolt = <100000>;
#endif
ports {
#ifdef GMSL_CAMERA_0
port@0 {
max9286_in0: endpoint {
remote-endpoint = <&fakra_con0>;
};
};
#endif
#ifdef GMSL_CAMERA_1
port@1 {
max9286_in1: endpoint{
remote-endpoint = <&fakra_con1>;
};
};
#endif
#ifdef GMSL_CAMERA_2
port@2 {
max9286_in2: endpoint {
remote-endpoint = <&fakra_con2>;
};
};
#endif
#ifdef GMSL_CAMERA_3
port@3 {
max9286_in3: endpoint {
remote-endpoint = <&fakra_con3>;
};
};
#endif
};
i2c-mux {
#ifdef GMSL_CAMERA_0
i2c@0 {
status = "okay";
camera@51 {
compatible = GMSL_CAMERA_MODEL;
reg = <0x51>, <0x61>;
port {
fakra_con0: endpoint {
remote-endpoint = <&max9286_in0>;
};
};
};
};
#endif
#ifdef GMSL_CAMERA_1
i2c@1 {
status = "okay";
camera@52 {
compatible = GMSL_CAMERA_MODEL;
reg = <0x52>, <0x62>;
port {
fakra_con1: endpoint {
remote-endpoint = <&max9286_in1>;
};
};
};
};
#endif
#ifdef GMSL_CAMERA_2
i2c@2 {
status = "okay";
camera@53 {
compatible = GMSL_CAMERA_MODEL;
reg = <0x53>, <0x63>;
port {
fakra_con2: endpoint {
remote-endpoint = <&max9286_in2>;
};
};
};
};
#endif
#ifdef GMSL_CAMERA_3
i2c@3 {
status = "okay";
camera@54 {
compatible = GMSL_CAMERA_MODEL;
reg = <0x54>, <0x64>;
port {
fakra_con3: endpoint {
remote-endpoint = <&max9286_in3>;
};
};
};
};
#endif
};
};
#endif /* ifdef GMSL_0 */
#ifdef GMSL_1
&vin4 {
status = "okay";
};
&vin5 {
status = "okay";
};
&vin6 {
status = "okay";
};
&vin7 {
status = "okay";
};
&gmsl1 {
status = "okay";
#if defined(GMSL_CAMERA_RDACM21)
maxim,reverse-channel-microvolt = <100000>;
#endif
ports {
#ifdef GMSL_CAMERA_4
port@0 {
max9286_in4: endpoint {
remote-endpoint = <&fakra_con4>;
};
};
#endif
#ifdef GMSL_CAMERA_5
port@1 {
max9286_in5: endpoint{
remote-endpoint = <&fakra_con5>;
};
};
#endif
#ifdef GMSL_CAMERA_6
port@2 {
max9286_in6: endpoint {
remote-endpoint = <&fakra_con6>;
};
};
#endif
#ifdef GMSL_CAMERA_7
port@3 {
max9286_in7: endpoint {
remote-endpoint = <&fakra_con7>;
};
};
#endif
};
i2c-mux {
#ifdef GMSL_CAMERA_4
i2c@0 {
status = "okay";
camera@55 {
compatible = GMSL_CAMERA_MODEL;
reg = <0x55>, <0x65>;
port {
fakra_con4: endpoint {
remote-endpoint = <&max9286_in4>;
};
};
};
};
#endif
#ifdef GMSL_CAMERA_5
i2c@1 {
status = "okay";
camera@56 {
compatible = GMSL_CAMERA_MODEL;
reg = <0x56>, <0x66>;
port {
fakra_con5: endpoint {
remote-endpoint = <&max9286_in5>;
};
};
};
};
#endif
#ifdef GMSL_CAMERA_6
i2c@2 {
status = "okay";
camera@57 {
compatible = GMSL_CAMERA_MODEL;
reg = <0x57>, <0x67>;
port {
fakra_con6: endpoint {
remote-endpoint = <&max9286_in6>;
};
};
};
};
#endif
#ifdef GMSL_CAMERA_7
i2c@3 {
status = "okay";
camera@58 {
compatible = GMSL_CAMERA_MODEL;
reg = <0x58>, <0x68>;
port {
fakra_con7: endpoint {
remote-endpoint = <&max9286_in7>;
};
};
};
};
#endif
};
};
#endif /* ifdef GMSL_1 */

12
arch/arm64/boot/dts/renesas/r8a77951.dtsi
View File

@ -2412,6 +2412,18 @@ ssi9: ssi-9 {
};
};
mlp: mlp@ec520000 {
compatible = "renesas,r8a7795-mlp",
"renesas,rcar-gen3-mlp";
reg = <0 0xec520000 0 0x800>;
interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 802>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 802>;
status = "disabled";
};
audma0: dma-controller@ec700000 {
compatible = "renesas,dmac-r8a7795",
"renesas,rcar-dmac";

12
arch/arm64/boot/dts/renesas/r8a77960.dtsi
View File

@ -2284,6 +2284,18 @@ ssiu97: ssiu-51 {
};
};
mlp: mlp@ec520000 {
compatible = "renesas,r8a7796-mlp",
"renesas,rcar-gen3-mlp";
reg = <0 0xec520000 0 0x800>;
interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 802>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 802>;
status = "disabled";
};
audma0: dma-controller@ec700000 {
compatible = "renesas,dmac-r8a7796",
"renesas,rcar-dmac";

39
arch/arm64/boot/dts/renesas/r8a77961.dtsi
View File

@ -2128,6 +2128,18 @@ ssiu97: ssiu-51 {
};
};
mlp: mlp@ec520000 {
compatible = "renesas,r8a77961-mlp",
"renesas,rcar-gen3-mlp";
reg = <0 0xec520000 0 0x800>;
interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 802>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 802>;
status = "disabled";
};
audma0: dma-controller@ec700000 {
compatible = "renesas,dmac-r8a77961",
"renesas,rcar-dmac";
@ -2722,6 +2734,33 @@ du_out_hdmi0: endpoint {
port@2 {
reg = <2>;
du_out_lvds0: endpoint {
remote-endpoint = <&lvds0_in>;
};
};
};
};
lvds0: lvds@feb90000 {
compatible = "renesas,r8a77961-lvds";
reg = <0 0xfeb90000 0 0x14>;
clocks = <&cpg CPG_MOD 727>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 727>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds0_in: endpoint {
remote-endpoint = <&du_out_lvds0>;
};
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};

12
arch/arm64/boot/dts/renesas/r8a77965.dtsi
View File

@ -2147,6 +2147,18 @@ ssi9: ssi-9 {
};
};
mlp: mlp@ec520000 {
compatible = "renesas,r8a77965-mlp",
"renesas,rcar-gen3-mlp";
reg = <0 0xec520000 0 0x800>;
interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 802>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 802>;
status = "disabled";
};
audma0: dma-controller@ec700000 {
compatible = "renesas,dmac-r8a77965",
"renesas,rcar-dmac";

102
arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
View File

@ -113,6 +113,20 @@ channel0 {
};
};
&csi40 {
status = "okay";
ports {
port@0 {
csi40_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&max9286_out0>;
};
};
};
};
&du {
clocks = <&cpg CPG_MOD 724>, <&x1_clk>;
clock-names = "du.0", "dclkin.0";
@ -172,6 +186,89 @@ adv7511_out: endpoint {
};
};
&i2c3 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
gmsl0: gmsl-deserializer@48 {
compatible = "maxim,max9286";
reg = <0x48>;
maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
enable-gpios = <&io_expander 0 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
};
port@2 {
reg = <2>;
};
port@3 {
reg = <3>;
};
port@4 {
reg = <4>;
max9286_out0: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi40_in>;
};
};
};
i2c-mux {
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
status = "disabled";
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
status = "disabled";
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
status = "disabled";
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
status = "disabled";
};
};
};
};
&lvds0 {
status = "okay";
@ -200,6 +297,11 @@ i2c0_pins: i2c0 {
function = "i2c0";
};
i2c3_pins: i2c3 {
groups = "i2c3_a";
function = "i2c3";
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";

191
arch/arm64/boot/dts/renesas/r8a77980-condor.dts
View File

@ -108,6 +108,34 @@ channel0 {
};
};
&csi40 {
status = "okay";
ports {
port@0 {
csi40_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&max9286_out0>;
};
};
};
};
&csi41 {
status = "okay";
ports {
port@0 {
csi41_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&max9286_out1>;
};
};
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&x1_clk>;
@ -200,6 +228,164 @@ adv7511_out: endpoint {
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
gmsl0: gmsl-deserializer@48 {
compatible = "maxim,max9286";
reg = <0x48>;
maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
enable-gpios = <&io_expander0 0 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
};
port@2 {
reg = <2>;
};
port@3 {
reg = <3>;
};
port@4 {
reg = <4>;
max9286_out0: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi40_in>;
};
};
};
i2c-mux {
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
status = "disabled";
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
status = "disabled";
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
status = "disabled";
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
status = "disabled";
};
};
};
gmsl1: gmsl-deserializer@4a {
compatible = "maxim,max9286";
reg = <0x4a>;
maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
enable-gpios = <&io_expander1 0 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
};
port@2 {
reg = <2>;
};
port@3 {
reg = <3>;
};
port@4 {
reg = <4>;
max9286_out1: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi41_in>;
};
};
};
i2c-mux {
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
status = "disabled";
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
status = "disabled";
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
status = "disabled";
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
status = "disabled";
};
};
};
};
&lvds0 {
status = "okay";
@ -256,6 +442,11 @@ i2c0_pins: i2c0 {
function = "i2c0";
};
i2c1_pins: i2c1 {
groups = "i2c1";
function = "i2c1";
};
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";

12
arch/arm64/boot/dts/renesas/r8a77990.dtsi
View File

@ -1682,6 +1682,18 @@ ssi9: ssi-9 {
};
};
mlp: mlp@ec520000 {
compatible = "renesas,r8a77990-mlp",
"renesas,rcar-gen3-mlp";
reg = <0 0xec520000 0 0x800>;
interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 802>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 802>;
status = "disabled";
};
audma0: dma-controller@ec700000 {
compatible = "renesas,dmac-r8a77990",
"renesas,rcar-dmac";

12
arch/arm64/boot/dts/renesas/r8a77995.dtsi
View File

@ -1132,6 +1132,18 @@ ssi4: ssi-4 {
};
};
mlp: mlp@ec520000 {
compatible = "renesas,r8a77995-mlp",
"renesas,rcar-gen3-mlp";
reg = <0 0xec520000 0 0x800>;
interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 802>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 802>;
status = "disabled";
};
audma0: dma-controller@ec700000 {
compatible = "renesas,dmac-r8a77995",
"renesas,rcar-dmac";

229
arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi
View File

@ -5,6 +5,63 @@
* Copyright (C) 2021 Glider bv
*/
&csi40 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csi40_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&max96712_out0>;
};
};
};
};
&csi42 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csi42_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&max96712_out1>;
};
};
};
};
&csi43 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csi43_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&max96712_out2>;
};
};
};
};
&i2c0 {
pca9654_a: gpio@21 {
compatible = "onnn,pca9654";
@ -34,3 +91,175 @@ eeprom@52 {
pagesize = <8>;
};
};
&i2c1 {
gmsl0: gmsl-deserializer@49 {
compatible = "maxim,max96712";
reg = <0x49>;
enable-gpios = <&pca9654_a 0 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@4 {
reg = <4>;
max96712_out0: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi40_in>;
};
};
};
};
gmsl1: gmsl-deserializer@4b {
compatible = "maxim,max96712";
reg = <0x4b>;
enable-gpios = <&pca9654_b 0 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@4 {
reg = <4>;
max96712_out1: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
lane-polarities = <0 0 0 0 1>;
remote-endpoint = <&csi42_in>;
};
};
};
};
gmsl2: gmsl-deserializer@6b {
compatible = "maxim,max96712";
reg = <0x6b>;
enable-gpios = <&pca9654_c 0 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@4 {
reg = <4>;
max96712_out2: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
lane-polarities = <0 0 0 0 1>;
remote-endpoint = <&csi43_in>;
};
};
};
};
};
&isp0 {
status = "okay";
};
&isp2 {
status = "okay";
};
&isp3 {
status = "okay";
};
&vin00 {
status = "okay";
};
&vin01 {
status = "okay";
};
&vin02 {
status = "okay";
};
&vin03 {
status = "okay";
};
&vin04 {
status = "okay";
};
&vin05 {
status = "okay";
};
&vin06 {
status = "okay";
};
&vin07 {
status = "okay";
};
&vin16 {
status = "okay";
};
&vin17 {
status = "okay";
};
&vin18 {
status = "okay";
};
&vin19 {
status = "okay";
};
&vin20 {
status = "okay";
};
&vin21 {
status = "okay";
};
&vin22 {
status = "okay";
};
&vin23 {
status = "okay";
};
&vin24 {
status = "okay";
};
&vin25 {
status = "okay";
};
&vin26 {
status = "okay";
};
&vin27 {
status = "okay";
};
&vin28 {
status = "okay";
};
&vin29 {
status = "okay";
};
&vin30 {
status = "okay";
};
&vin31 {
status = "okay";
};

15
arch/arm64/boot/dts/renesas/r8a779a0.dtsi
View File

@ -340,6 +340,21 @@ tsc: thermal@e6190000 {
#thermal-sensor-cells = <1>;
};
intc_ex: interrupt-controller@e61c0000 {
compatible = "renesas,intc-ex-r8a779a0", "renesas,irqc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0 0xe61c0000 0 0x200>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_CORE R8A779A0_CLK_CP>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
};
tmu0: timer@e61e0000 {
compatible = "renesas,tmu-r8a779a0", "renesas,tmu";
reg = <0 0xe61e0000 0 0x30>;

70
arch/arm64/boot/dts/renesas/r8a779f0.dtsi
View File

@ -94,6 +94,76 @@ scif3: serial@e6c50000 {
status = "disabled";
};
dmac0: dma-controller@e7350000 {
compatible = "renesas,dmac-r8a779f0",
"renesas,rcar-gen4-dmac";
reg = <0 0xe7350000 0 0x1000>,
<0 0xe7300000 0 0x10000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3", "ch4",
"ch5", "ch6", "ch7", "ch8", "ch9",
"ch10", "ch11", "ch12", "ch13",
"ch14", "ch15";
clocks = <&cpg CPG_MOD 709>;
clock-names = "fck";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 709>;
#dma-cells = <1>;
dma-channels = <16>;
};
dmac1: dma-controller@e7351000 {
compatible = "renesas,dmac-r8a779f0",
"renesas,rcar-gen4-dmac";
reg = <0 0xe7351000 0 0x1000>,
<0 0xe7310000 0 0x10000>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3", "ch4",
"ch5", "ch6", "ch7", "ch8", "ch9",
"ch10", "ch11", "ch12", "ch13",
"ch14", "ch15";
clocks = <&cpg CPG_MOD 710>;
clock-names = "fck";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 710>;
#dma-cells = <1>;
dma-channels = <16>;
};
gic: interrupt-controller@f1000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;

32
arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi Normal file
View File

@ -0,0 +1,32 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2LC R9A07G044C1 SoC specific parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r9a07g044.dtsi"
/ {
compatible = "renesas,r9a07g044c1", "renesas,r9a07g044";
cpus {
/delete-node/ cpu-map;
/delete-node/ cpu@100;
};
timer {
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
};
&soc {
/delete-node/ ssi@1004a800;
/delete-node/ serial@1004c800;
/delete-node/ adc@10059000;
/delete-node/ ethernet@11c30000;
};

91
arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts Normal file
View File

@ -0,0 +1,91 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2LC SMARC EVK board
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r9a07g044c2.dtsi"
#include "rzg2lc-smarc.dtsi"
/ {
model = "Renesas SMARC EVK based on r9a07g044c2";
compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044";
};
&ehci0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&ehci1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&hsusb {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&i2c0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&i2c1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&i2c3 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&ohci0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&ohci1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&phyrst {
status = "disabled";
};
&spi1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&ssi0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&usb2_phy0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&usb2_phy1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};

20
arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi Normal file
View File

@ -0,0 +1,20 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2LC R9A07G044C2 SoC specific parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r9a07g044.dtsi"
/ {
compatible = "renesas,r9a07g044c2", "renesas,r9a07g044";
};
&soc {
/delete-node/ ssi@1004a800;
/delete-node/ serial@1004c800;
/delete-node/ adc@10059000;
/delete-node/ ethernet@11c30000;
};

2
arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
View File

@ -8,6 +8,8 @@
/dts-v1/;
#include "r9a07g044l2.dtsi"
#include "rzg2l-smarc-som.dtsi"
#include "rzg2l-smarc-pinfunction.dtsi"
#include "rz-smarc-common.dtsi"
#include "rzg2l-smarc.dtsi"
/ {

491
arch/arm64/boot/dts/renesas/r9a07g054.dtsi Normal file
View File

@ -0,0 +1,491 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/V2L SoC
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r9a07g054-cpg.h>
/ {
compatible = "renesas,r9a07g054";
#address-cells = <2>;
#size-cells = <2>;
audio_clk1: audio_clk1 {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by boards that provide it */
clock-frequency = <0>;
};
audio_clk2: audio_clk2 {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by boards that provide it */
clock-frequency = <0>;
};
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a55";
reg = <0>;
device_type = "cpu";
#cooling-cells = <2>;
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
};
cpu1: cpu@100 {
compatible = "arm,cortex-a55";
reg = <0x100>;
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
};
L3_CA55: cache-controller-0 {
compatible = "cache";
cache-unified;
cache-size = <0x40000>;
};
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
ssi0: ssi@10049c00 {
reg = <0 0x10049c00 0 0x400>;
#sound-dai-cells = <0>;
/* place holder */
};
spi1: spi@1004b000 {
reg = <0 0x1004b000 0 0x400>;
#address-cells = <1>;
#size-cells = <0>;
/* place holder */
};
scif0: serial@1004b800 {
compatible = "renesas,scif-r9a07g054",
"renesas,scif-r9a07g044";
reg = <0 0x1004b800 0 0x400>;
interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G054_SCIF0_CLK_PCK>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A07G054_SCIF0_RST_SYSTEM_N>;
status = "disabled";
};
scif1: serial@1004bc00 {
compatible = "renesas,scif-r9a07g054",
"renesas,scif-r9a07g044";
reg = <0 0x1004bc00 0 0x400>;
interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G054_SCIF1_CLK_PCK>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A07G054_SCIF1_RST_SYSTEM_N>;
status = "disabled";
};
scif2: serial@1004c000 {
compatible = "renesas,scif-r9a07g054",
"renesas,scif-r9a07g044";
reg = <0 0x1004c000 0 0x400>;
interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G054_SCIF2_CLK_PCK>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A07G054_SCIF2_RST_SYSTEM_N>;
status = "disabled";
};
scif3: serial@1004c400 {
compatible = "renesas,scif-r9a07g054",
"renesas,scif-r9a07g044";
reg = <0 0x1004c400 0 0x400>;
interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G054_SCIF3_CLK_PCK>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A07G054_SCIF3_RST_SYSTEM_N>;
status = "disabled";
};
scif4: serial@1004c800 {
compatible = "renesas,scif-r9a07g054",
"renesas,scif-r9a07g044";
reg = <0 0x1004c800 0 0x400>;
interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G054_SCIF4_CLK_PCK>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A07G054_SCIF4_RST_SYSTEM_N>;
status = "disabled";
};
sci0: serial@1004d000 {
compatible = "renesas,r9a07g054-sci", "renesas,sci";
reg = <0 0x1004d000 0 0x400>;
interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A07G054_SCI0_RST>;
status = "disabled";
};
sci1: serial@1004d400 {
compatible = "renesas,r9a07g054-sci", "renesas,sci";
reg = <0 0x1004d400 0 0x400>;
interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A07G054_SCI1_RST>;
status = "disabled";
};
canfd: can@10050000 {
reg = <0 0x10050000 0 0x8000>;
/* place holder */
};
i2c0: i2c@10058000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x10058000 0 0x400>;
/* place holder */
};
i2c1: i2c@10058400 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x10058400 0 0x400>;
/* place holder */
};
i2c3: i2c@10058c00 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x10058c00 0 0x400>;
/* place holder */
};
adc: adc@10059000 {
reg = <0 0x10059000 0 0x400>;
/* place holder */
};
sbc: spi@10060000 {
reg = <0 0x10060000 0 0x10000>,
<0 0x20000000 0 0x10000000>,
<0 0x10070000 0 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
/* place holder */
};
cpg: clock-controller@11010000 {
compatible = "renesas,r9a07g054-cpg";
reg = <0 0x11010000 0 0x10000>;
clocks = <&extal_clk>;
clock-names = "extal";
#clock-cells = <2>;
#reset-cells = <1>;
#power-domain-cells = <0>;
};
sysc: system-controller@11020000 {
compatible = "renesas,r9a07g054-sysc";
reg = <0 0x11020000 0 0x10000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "lpm_int", "ca55stbydone_int",
"cm33stbyr_int", "ca55_deny";
status = "disabled";
};
pinctrl: pinctrl@11030000 {
compatible = "renesas,r9a07g054-pinctrl",
"renesas,r9a07g044-pinctrl";
reg = <0 0x11030000 0 0x10000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 392>;
clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>;
power-domains = <&cpg>;
resets = <&cpg R9A07G054_GPIO_RSTN>,
<&cpg R9A07G054_GPIO_PORT_RESETN>,
<&cpg R9A07G054_GPIO_SPARE_RESETN>;
};
dmac: dma-controller@11820000 {
compatible = "renesas,r9a07g054-dmac",
"renesas,rz-dmac";
reg = <0 0x11820000 0 0x10000>,
<0 0x11830000 0 0x10000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>,
<&cpg CPG_MOD R9A07G054_DMAC_PCLK>;
power-domains = <&cpg>;
resets = <&cpg R9A07G054_DMAC_ARESETN>,
<&cpg R9A07G054_DMAC_RST_ASYNC>;
#dma-cells = <1>;
dma-channels = <16>;
};
gpu: gpu@11840000 {
reg = <0x0 0x11840000 0x0 0x10000>;
/* place holder */
};
gic: interrupt-controller@11900000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0x11900000 0 0x40000>,
<0x0 0x11940000 0 0x60000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
sdhi0: mmc@11c00000 {
reg = <0x0 0x11c00000 0 0x10000>;
/* place holder */
};
sdhi1: mmc@11c10000 {
reg = <0x0 0x11c10000 0 0x10000>;
/* place holder */
};
eth0: ethernet@11c20000 {
compatible = "renesas,r9a07g054-gbeth",
"renesas,rzg2l-gbeth";
reg = <0 0x11c20000 0 0x10000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mux", "fil", "arp_ns";
phy-mode = "rgmii";
clocks = <&cpg CPG_MOD R9A07G054_ETH0_CLK_AXI>,
<&cpg CPG_MOD R9A07G054_ETH0_CLK_CHI>,
<&cpg CPG_CORE R9A07G054_CLK_HP>;
clock-names = "axi", "chi", "refclk";
resets = <&cpg R9A07G054_ETH0_RST_HW_N>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
eth1: ethernet@11c30000 {
compatible = "renesas,r9a07g054-gbeth",
"renesas,rzg2l-gbeth";
reg = <0 0x11c30000 0 0x10000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mux", "fil", "arp_ns";
phy-mode = "rgmii";
clocks = <&cpg CPG_MOD R9A07G054_ETH1_CLK_AXI>,
<&cpg CPG_MOD R9A07G054_ETH1_CLK_CHI>,
<&cpg CPG_CORE R9A07G054_CLK_HP>;
clock-names = "axi", "chi", "refclk";
resets = <&cpg R9A07G054_ETH1_RST_HW_N>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
phyrst: usbphy-ctrl@11c40000 {
reg = <0 0x11c40000 0 0x10000>;
/* place holder */
};
ohci0: usb@11c50000 {
reg = <0 0x11c50000 0 0x100>;
/* place holder */
};
ohci1: usb@11c70000 {
reg = <0 0x11c70000 0 0x100>;
/* place holder */
};
ehci0: usb@11c50100 {
reg = <0 0x11c50100 0 0x100>;
/* place holder */
};
ehci1: usb@11c70100 {
reg = <0 0x11c70100 0 0x100>;
/* place holder */
};
usb2_phy0: usb-phy@11c50200 {
reg = <0 0x11c50200 0 0x700>;
/* place holder */
};
usb2_phy1: usb-phy@11c70200 {
reg = <0 0x11c70200 0 0x700>;
/* place holder */
};
hsusb: usb@11c60000 {
reg = <0 0x11c60000 0 0x10000>;
/* place holder */
};
wdt0: watchdog@12800800 {
reg = <0 0x12800800 0 0x400>;
/* place holder */
};
wdt1: watchdog@12800c00 {
reg = <0 0x12800C00 0 0x400>;
/* place holder */
};
wdt2: watchdog@12800400 {
reg = <0 0x12800400 0 0x400>;
/* place holder */
};
ostm0: timer@12801000 {
reg = <0x0 0x12801000 0x0 0x400>;
/* place holder */
};
ostm1: timer@12801400 {
reg = <0x0 0x12801400 0x0 0x400>;
/* place holder */
};
ostm2: timer@12801800 {
reg = <0x0 0x12801800 0x0 0x400>;
/* place holder */
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
};

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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/V2L R9A07G054L1 SoC specific parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r9a07g054.dtsi"
/ {
compatible = "renesas,r9a07g054l1", "renesas,r9a07g054";
cpus {
/delete-node/ cpu-map;
/delete-node/ cpu@100;
};
timer {
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
};

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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2L SMARC EVK board
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r9a07g054l2.dtsi"
#include "rzg2l-smarc-som.dtsi"
#include "rzg2l-smarc-pinfunction.dtsi"
#include "rz-smarc-common.dtsi"
#include "rzg2l-smarc.dtsi"
/ {
model = "Renesas SMARC EVK based on r9a07g054l2";
compatible = "renesas,smarc-evk", "renesas,r9a07g054l2", "renesas,r9a07g054";
};
&pinctrl {
/delete-node/ can0-stb;
/delete-node/ can1-stb;
/delete-node/ gpio-sd0-pwr-en-hog;
/delete-node/ sd0-dev-sel-hog;
/delete-node/ sd1-pwr-en-hog;
};

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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/V2L R9A07G054L2 SoC specific parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r9a07g054.dtsi"
/ {
compatible = "renesas,r9a07g054l2", "renesas,r9a07g054";
};

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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/{G2L,G2LC,V2L} SMARC EVK common parts
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/*
* SSI-WM8978
*
* This command is required when Playback/Capture
*
* amixer cset name='Left Input Mixer L2 Switch' on
* amixer cset name='Right Input Mixer R2 Switch' on
* amixer cset name='Headphone Playback Volume' 100
* amixer cset name='PCM Volume' 100%
* amixer cset name='Input PGA Volume' 25
*
*/
/ {
aliases {
serial0 = &scif0;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c3 = &i2c3;
};
chosen {
stdout-path = "serial0:115200n8";
};
audio_mclock: audio_mclock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
};
snd_rzg2l: sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&cpu_dai>;
simple-audio-card,frame-master = <&cpu_dai>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,widgets = "Microphone", "Microphone Jack";
simple-audio-card,routing =
"L2", "Mic Bias",
"R2", "Mic Bias",
"Mic Bias", "Microphone Jack";
cpu_dai: simple-audio-card,cpu {
sound-dai = <&ssi0>;
};
codec_dai: simple-audio-card,codec {
clocks = <&audio_mclock>;
sound-dai = <&wm8978>;
};
};
usb0_vbus_otg: regulator-usb0-vbus-otg {
compatible = "regulator-fixed";
regulator-name = "USB0_VBUS_OTG";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vccq_sdhi1: regulator-vccq-sdhi1 {
compatible = "regulator-gpio";
regulator-name = "SDHI1 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1>, <1800000 0>;
};
};
&audio_clk1{
clock-frequency = <11289600>;
};
&audio_clk2{
clock-frequency = <12288000>;
};
&canfd {
pinctrl-0 = <&can0_pins &can1_pins>;
pinctrl-names = "default";
status = "okay";
channel0 {
status = "okay";
};
channel1 {
status = "okay";
};
};
&ehci0 {
dr_mode = "otg";
status = "okay";
};
&ehci1 {
status = "okay";
};
&hsusb {
dr_mode = "otg";
status = "okay";
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
};
&i2c3 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
clock-frequency = <400000>;
status = "okay";
wm8978: codec@1a {
compatible = "wlf,wm8978";
#sound-dai-cells = <0>;
reg = <0x1a>;
};
};
&ohci0 {
dr_mode = "otg";
status = "okay";
};
&ohci1 {
status = "okay";
};
&phyrst {
status = "okay";
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
status = "okay";
};
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
pinctrl-1 = <&sdhi1_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&vccq_sdhi1>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&spi1 {
pinctrl-0 = <&spi1_pins>;
pinctrl-names = "default";
status = "okay";
};
&ssi0 {
pinctrl-0 = <&ssi0_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
vbus-supply = <&usb0_vbus_otg>;
status = "okay";
};
&usb2_phy1 {
pinctrl-0 = <&usb1_pins>;
pinctrl-names = "default";
status = "okay";
};

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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/{G2L,V2L} SMARC pincontrol parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
&pinctrl {
pinctrl-0 = <&sound_clk_pins>;
pinctrl-names = "default";
can0_pins: can0 {
pinmux = <RZG2L_PORT_PINMUX(10, 1, 2)>, /* TX */
<RZG2L_PORT_PINMUX(11, 0, 2)>; /* RX */
};
/* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
can0-stb {
gpio-hog;
gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_HIGH>;
output-low;
line-name = "can0_stb";
};
can1_pins: can1 {
pinmux = <RZG2L_PORT_PINMUX(12, 1, 2)>, /* TX */
<RZG2L_PORT_PINMUX(13, 0, 2)>; /* RX */
};
/* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
can1-stb {
gpio-hog;
gpios = <RZG2L_GPIO(42, 3) GPIO_ACTIVE_HIGH>;
output-low;
line-name = "can1_stb";
};
i2c0_pins: i2c0 {
pins = "RIIC0_SDA", "RIIC0_SCL";
input-enable;
};
i2c1_pins: i2c1 {
pins = "RIIC1_SDA", "RIIC1_SCL";
input-enable;
};
i2c3_pins: i2c3 {
pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */
<RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
};
scif0_pins: scif0 {
pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
};
scif2_pins: scif2 {
pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(48, 1, 1)>, /* RxD */
<RZG2L_PORT_PINMUX(48, 3, 1)>, /* CTS# */
<RZG2L_PORT_PINMUX(48, 4, 1)>; /* RTS# */
};
sd1-pwr-en-hog {
gpio-hog;
gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "sd1_pwr_en";
};
sdhi1_pins: sd1 {
sd1_data {
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
power-source = <3300>;
};
sd1_ctrl {
pins = "SD1_CLK", "SD1_CMD";
power-source = <3300>;
};
sd1_mux {
pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
};
};
sdhi1_pins_uhs: sd1_uhs {
sd1_data_uhs {
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
power-source = <1800>;
};
sd1_ctrl_uhs {
pins = "SD1_CLK", "SD1_CMD";
power-source = <1800>;
};
sd1_mux_uhs {
pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
};
};
sound_clk_pins: sound_clk {
pins = "AUDIO_CLK1", "AUDIO_CLK2";
input-enable;
};
spi1_pins: spi1 {
pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */
<RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */
<RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */
<RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */
};
ssi0_pins: ssi0 {
pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
<RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */
<RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */
<RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */
};
usb0_pins: usb0 {
pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */
<RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */
<RZG2L_PORT_PINMUX(5, 1, 1)>; /* OTG_ID */
};
usb1_pins: usb1 {
pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */
<RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */
};
};

2
arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
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@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2L SMARC SOM common parts
* Device Tree Source for the RZ/{G2L,V2L} SMARC SOM common parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/

322
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
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@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2L SMARC EVK common parts
* Device Tree Source for the RZ/{G2L,V2L} SMARC EVK common parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
@ -8,291 +8,13 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/*
* SSI-WM8978
*
* This command is required when Playback/Capture
*
* amixer cset name='Left Input Mixer L2 Switch' on
* amixer cset name='Right Input Mixer R2 Switch' on
* amixer cset name='Headphone Playback Volume' 100
* amixer cset name='PCM Volume' 100%
* amixer cset name='Input PGA Volume' 25
*
*/
/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */
#define PMOD1_SER0 1
/ {
aliases {
serial0 = &scif0;
serial1 = &scif2;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c3 = &i2c3;
};
chosen {
stdout-path = "serial0:115200n8";
};
audio_mclock: audio_mclock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
};
snd_rzg2l: sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&cpu_dai>;
simple-audio-card,frame-master = <&cpu_dai>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,widgets = "Microphone", "Microphone Jack";
simple-audio-card,routing =
"L2", "Mic Bias",
"R2", "Mic Bias",
"Mic Bias", "Microphone Jack";
cpu_dai: simple-audio-card,cpu {
sound-dai = <&ssi0>;
};
codec_dai: simple-audio-card,codec {
clocks = <&audio_mclock>;
sound-dai = <&wm8978>;
};
};
usb0_vbus_otg: regulator-usb0-vbus-otg {
compatible = "regulator-fixed";
regulator-name = "USB0_VBUS_OTG";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vccq_sdhi1: regulator-vccq-sdhi1 {
compatible = "regulator-gpio";
regulator-name = "SDHI1 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1>, <1800000 0>;
};
};
&audio_clk1{
clock-frequency = <11289600>;
};
&audio_clk2{
clock-frequency = <12288000>;
};
&canfd {
pinctrl-0 = <&can0_pins &can1_pins>;
pinctrl-names = "default";
status = "okay";
channel0 {
status = "okay";
};
channel1 {
status = "okay";
};
};
&ehci0 {
dr_mode = "otg";
status = "okay";
};
&ehci1 {
status = "okay";
};
&hsusb {
dr_mode = "otg";
status = "okay";
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
};
&i2c3 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
clock-frequency = <400000>;
status = "okay";
wm8978: codec@1a {
compatible = "wlf,wm8978";
#sound-dai-cells = <0>;
reg = <0x1a>;
};
};
&ohci0 {
dr_mode = "otg";
status = "okay";
};
&ohci1 {
status = "okay";
};
&phyrst {
status = "okay";
};
&pinctrl {
pinctrl-0 = <&sound_clk_pins>;
pinctrl-names = "default";
can0_pins: can0 {
pinmux = <RZG2L_PORT_PINMUX(10, 1, 2)>, /* TX */
<RZG2L_PORT_PINMUX(11, 0, 2)>; /* RX */
};
/* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
can0-stb {
gpio-hog;
gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_HIGH>;
output-low;
line-name = "can0_stb";
};
can1_pins: can1 {
pinmux = <RZG2L_PORT_PINMUX(12, 1, 2)>, /* TX */
<RZG2L_PORT_PINMUX(13, 0, 2)>; /* RX */
};
/* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
can1-stb {
gpio-hog;
gpios = <RZG2L_GPIO(42, 3) GPIO_ACTIVE_HIGH>;
output-low;
line-name = "can1_stb";
};
i2c0_pins: i2c0 {
pins = "RIIC0_SDA", "RIIC0_SCL";
input-enable;
};
i2c1_pins: i2c1 {
pins = "RIIC1_SDA", "RIIC1_SCL";
input-enable;
};
i2c3_pins: i2c3 {
pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */
<RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
};
scif0_pins: scif0 {
pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
};
scif2_pins: scif2 {
pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(48, 1, 1)>, /* RxD */
<RZG2L_PORT_PINMUX(48, 3, 1)>, /* CTS# */
<RZG2L_PORT_PINMUX(48, 4, 1)>; /* RTS# */
};
sd1-pwr-en-hog {
gpio-hog;
gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "sd1_pwr_en";
};
sdhi1_pins: sd1 {
sd1_data {
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
power-source = <3300>;
};
sd1_ctrl {
pins = "SD1_CLK", "SD1_CMD";
power-source = <3300>;
};
sd1_mux {
pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
};
};
sdhi1_pins_uhs: sd1_uhs {
sd1_data_uhs {
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
power-source = <1800>;
};
sd1_ctrl_uhs {
pins = "SD1_CLK", "SD1_CMD";
power-source = <1800>;
};
sd1_mux_uhs {
pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
};
};
sound_clk_pins: sound_clk {
pins = "AUDIO_CLK1", "AUDIO_CLK2";
input-enable;
};
spi1_pins: spi1 {
pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */
<RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */
<RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */
<RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */
};
ssi0_pins: ssi0 {
pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
<RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */
<RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */
<RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */
};
usb0_pins: usb0 {
pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */
<RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */
<RZG2L_PORT_PINMUX(5, 1, 1)>; /* OTG_ID */
};
usb1_pins: usb1 {
pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */
<RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */
};
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
status = "okay";
};
/*
@ -311,45 +33,3 @@ &scif2 {
status = "okay";
};
#endif
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
pinctrl-1 = <&sdhi1_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&vccq_sdhi1>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&spi1 {
pinctrl-0 = <&spi1_pins>;
pinctrl-names = "default";
status = "okay";
};
&ssi0 {
pinctrl-0 = <&ssi0_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
vbus-supply = <&usb0_vbus_otg>;
status = "okay";
};
&usb2_phy1 {
pinctrl-0 = <&usb1_pins>;
pinctrl-names = "default";
status = "okay";
};

94
arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi Normal file
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@ -0,0 +1,94 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2LC SMARC pincontrol parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
&pinctrl {
pinctrl-0 = <&sound_clk_pins>;
pinctrl-names = "default";
scif0_pins: scif0 {
pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
};
#if SW_SCIF_CAN
/* SW8 should be at position 2->1 */
can1_pins: can1 {
pinmux = <RZG2L_PORT_PINMUX(40, 0, 3)>, /* TxD */
<RZG2L_PORT_PINMUX(40, 1, 3)>; /* RxD */
};
#endif
scif1_pins: scif1 {
pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */
<RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */
<RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */
};
#if SW_RSPI_CAN
/* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
can1-stb {
gpio-hog;
gpios = <RZG2L_GPIO(44, 3) GPIO_ACTIVE_HIGH>;
output-low;
line-name = "can1_stb";
};
can1_pins: can1 {
pinmux = <RZG2L_PORT_PINMUX(44, 0, 3)>, /* TxD */
<RZG2L_PORT_PINMUX(44, 1, 3)>; /* RxD */
};
#endif
sd1-pwr-en-hog {
gpio-hog;
gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "sd1_pwr_en";
};
sdhi1_pins: sd1 {
sd1_data {
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
power-source = <3300>;
};
sd1_ctrl {
pins = "SD1_CLK", "SD1_CMD";
power-source = <3300>;
};
sd1_mux {
pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
};
};
sdhi1_pins_uhs: sd1_uhs {
sd1_data_uhs {
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
power-source = <1800>;
};
sd1_ctrl_uhs {
pins = "SD1_CLK", "SD1_CMD";
power-source = <1800>;
};
sd1_mux_uhs {
pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
};
};
sound_clk_pins: sound_clk {
pins = "AUDIO_CLK1", "AUDIO_CLK2";
input-enable;
};
};

208
arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi Normal file
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@ -0,0 +1,208 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2LC SMARC SOM common parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/ {
aliases {
ethernet0 = &eth0;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
states = <3300000 1>, <1800000 0>;
regulator-boot-on;
gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
regulator-always-on;
};
};
&eth0 {
pinctrl-0 = <&eth0_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
phy0: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
reg = <7>;
rxc-skew-psec = <2400>;
txc-skew-psec = <2400>;
rxdv-skew-psec = <0>;
txdv-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
rxd3-skew-psec = <0>;
txd0-skew-psec = <0>;
txd1-skew-psec = <0>;
txd2-skew-psec = <0>;
txd3-skew-psec = <0>;
};
};
&extal_clk {
clock-frequency = <24000000>;
};
&pinctrl {
eth0_pins: eth0 {
pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
<RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
<RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
<RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
<RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
<RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
<RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
<RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
<RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
<RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
<RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
<RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
<RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
<RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
<RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
};
gpio-sd0-pwr-en-hog {
gpio-hog;
gpios = <RZG2L_GPIO(18, 1) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "gpio_sd0_pwr_en";
};
/*
* SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
* The below switch logic can be used to select the device between
* eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
* SW1[2] should be at OFF position to enable 64 GB eMMC
* SW1[2] should be at position ON to enable uSD card CN3
*/
gpio-sd0-dev-sel-hog {
gpio-hog;
gpios = <RZG2L_GPIO(40, 2) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "gpio_sd0_dev_sel";
};
sdhi0_emmc_pins: sd0emmc {
sd0_emmc_data {
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
"SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
power-source = <1800>;
};
sd0_emmc_ctrl {
pins = "SD0_CLK", "SD0_CMD";
power-source = <1800>;
};
sd0_emmc_rst {
pins = "SD0_RST#";
power-source = <1800>;
};
};
sdhi0_pins: sd0 {
sd0_data {
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
power-source = <3300>;
};
sd0_ctrl {
pins = "SD0_CLK", "SD0_CMD";
power-source = <3300>;
};
sd0_mux {
pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */
};
};
sdhi0_pins_uhs: sd0_uhs {
sd0_data_uhs {
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
power-source = <1800>;
};
sd0_ctrl_uhs {
pins = "SD0_CLK", "SD0_CMD";
power-source = <1800>;
};
sd0_mux_uhs {
pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */
};
};
};
#if (!SW_SD0_DEV_SEL)
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&vccq_sdhi0>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
#endif
#if SW_SD0_DEV_SEL
&sdhi0 {
pinctrl-0 = <&sdhi0_emmc_pins>;
pinctrl-1 = <&sdhi0_emmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
mmc-hs200-1_8v;
non-removable;
fixed-emmc-driver-type = <1>;
status = "okay";
};
#endif

77
arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi Normal file
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@ -0,0 +1,77 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2LC SMARC EVK parts
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/*
* DIP-Switch SW1 setting on SoM
* 1 : High; 0: Low
* SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD)
* SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1)
* SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1)
* SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0)
* Please change below macros according to SW1 setting
*/
#define SW_SD0_DEV_SEL 1
#define SW_SCIF_CAN 0
#if (SW_SCIF_CAN)
/* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */
#define SW_RSPI_CAN 0
#else
/* Please set SW_RSPI_CAN. Default value is 1 */
#define SW_RSPI_CAN 1
#endif
#if (SW_SCIF_CAN & SW_RSPI_CAN)
#error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing"
#endif
#include "rzg2lc-smarc-som.dtsi"
#include "rzg2lc-smarc-pinfunction.dtsi"
#include "rz-smarc-common.dtsi"
/* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */
#define PMOD1_SER0 1
/ {
aliases {
serial1 = &scif1;
};
};
#if (SW_SCIF_CAN || SW_RSPI_CAN)
&canfd {
pinctrl-0 = <&can1_pins>;
/delete-node/ channel@0;
};
#else
&canfd {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
#endif
/*
* To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
* SW1 should be at position 2->3 so that SER0_CTS# line is activated
* SW2 should be at position 2->3 so that SER0_TX line is activated
* SW3 should be at position 2->3 so that SER0_RX line is activated
* SW4 should be at position 2->3 so that SER0_RTS# line is activated
*/
#if (!SW_SCIF_CAN && PMOD1_SER0)
&scif1 {
pinctrl-0 = <&scif1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
#endif

133
arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
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@ -26,6 +26,38 @@ clksndsel: clksndsel {
select-gpios = <&gpio_exp_75 13 GPIO_ACTIVE_HIGH>;
};
hdmi1-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi1_con: endpoint {
remote-endpoint = <&adv7513_out>;
};
};
};
accel_3v3: regulator-acc-3v3 {
compatible = "regulator-fixed";
regulator-name = "accel-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
hdmi_1v8: regulator-hdmi-1v8 {
compatible = "regulator-fixed";
regulator-name = "hdmi-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
hdmi_3v3: regulator-hdmi-3v3 {
compatible = "regulator-fixed";
regulator-name = "hdmi-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
snd_3p3v: regulator-snd_3p3v {
compatible = "regulator-fixed";
regulator-name = "snd-3.3v";
@ -65,6 +97,10 @@ &can1 {
status = "okay";
};
&du_out_rgb {
remote-endpoint = <&adv7513_in>;
};
&ehci0 {
dr_mode = "otg";
status = "okay";
@ -91,12 +127,72 @@ i2cswitch2: i2c-switch@71 {
reg = <0x71>;
reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
/* HDMIoSDA, HDMIoSCL */
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
hdmi@3d {
compatible = "adi,adv7513";
reg = <0x3d>;
pinctrl-0 = <&hdmi1_pins>;
pinctrl-names = "default";
interrupt-parent = <&gpio2>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
clocks = <&cs2000>;
clock-names = "cec";
pd-gpios = <&gpio_exp_75 5 GPIO_ACTIVE_LOW>;
avdd-supply = <&hdmi_1v8>;
dvdd-supply = <&hdmi_1v8>;
pvdd-supply = <&hdmi_1v8>;
dvdd-3v-supply = <&hdmi_3v3>;
bgvdd-supply = <&hdmi_1v8>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7513_in: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
port@1 {
reg = <1>;
adv7513_out: endpoint {
remote-endpoint = <&hdmi1_con>;
};
};
};
};
};
/* Audio_SDA, Audio_SCL */
i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
accelerometer@1d {
compatible = "st,lsm9ds0-imu";
reg = <0x1d>;
vdd-supply = <&accel_3v3>;
vddio-supply = <&accel_3v3>;
};
pcm3168a: audio-codec@44 {
#sound-dai-cells = <0>;
compatible = "ti,pcm3168a";
@ -131,6 +227,14 @@ pcm3168a_endpoint_c: endpoint {
};
};
};
gyroscope@6b {
compatible = "st,lsm9ds0-gyro";
reg = <0x6b>;
vdd-supply = <&accel_3v3>;
vddio-supply = <&accel_3v3>;
};
};
};
@ -264,6 +368,19 @@ can1_pins: can1 {
function = "can1";
};
hdmi1_pins: hdmi1 {
adv7513-interrupt {
pins = "GP_2_14";
bias-pull-up;
};
du {
groups = "du_rgb888", "du_sync", "du_clk_out_0",
"du_disp";
function = "du";
};
};
hscif0_pins: hscif0 {
groups = "hscif0_data", "hscif0_ctrl";
function = "hscif0";
@ -302,12 +419,9 @@ rsnd_port2: port@2 {
reg = <2>;
rsnd_for_pcm3168a_play: endpoint {
remote-endpoint = <&pcm3168a_endpoint_p>;
dai-format = "i2s";
bitclock-master = <&rsnd_for_pcm3168a_play>;
frame-master = <&rsnd_for_pcm3168a_play>;
bitclock-master;
frame-master;
dai-tdm-slot-num = <8>;
playback = <&ssi3>;
};
};
@ -315,12 +429,9 @@ rsnd_port3: port@3 {
reg = <3>;
rsnd_for_pcm3168a_capture: endpoint {
remote-endpoint = <&pcm3168a_endpoint_c>;
dai-format = "i2s";
bitclock-master = <&rsnd_for_pcm3168a_capture>;
frame-master = <&rsnd_for_pcm3168a_capture>;
bitclock-master;
frame-master;
dai-tdm-slot-num = <6>;
capture = <&ssi4>;
};
};
@ -360,7 +471,7 @@ wlcore: wlcore@2 {
};
&sound_card {
dais = <&rsnd_port0 /* ak4613 */
links = <&rsnd_port0 /* ak4613 */
&rsnd_port1 /* HDMI0 */
&rsnd_port2 /* pcm3168a playback */
&rsnd_port3 /* pcm3168a capture */

18
arch/arm64/boot/dts/renesas/ulcb.dtsi
View File

@ -95,10 +95,10 @@ reg_3p3v: regulator1 {
};
sound_card: sound {
compatible = "audio-graph-card";
compatible = "audio-graph-card2";
label = "rcar-sound";
dais = <&rsnd_port0 /* ak4613 */
links = <&rsnd_port0 /* ak4613 */
&rsnd_port1 /* HDMI0 */
>;
};
@ -408,11 +408,8 @@ rsnd_port0: port@0 {
reg = <0>;
rsnd_for_ak4613: endpoint {
remote-endpoint = <&ak4613_endpoint>;
dai-format = "left_j";
bitclock-master = <&rsnd_for_ak4613>;
frame-master = <&rsnd_for_ak4613>;
bitclock-master;
frame-master;
playback = <&ssi0>, <&src0>, <&dvc0>;
capture = <&ssi1>, <&src1>, <&dvc1>;
};
@ -421,11 +418,8 @@ rsnd_port1: port@1 {
reg = <1>;
rsnd_for_hdmi: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_for_hdmi>;
frame-master = <&rsnd_for_hdmi>;
bitclock-master;
frame-master;
playback = <&ssi2>;
};
};

229
include/dt-bindings/clock/r9a07g054-cpg.h Normal file
View File

@ -0,0 +1,229 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__
#define __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* R9A07G054 CPG Core Clocks */
#define R9A07G054_CLK_I 0
#define R9A07G054_CLK_I2 1
#define R9A07G054_CLK_G 2
#define R9A07G054_CLK_S0 3
#define R9A07G054_CLK_S1 4
#define R9A07G054_CLK_SPI0 5
#define R9A07G054_CLK_SPI1 6
#define R9A07G054_CLK_SD0 7
#define R9A07G054_CLK_SD1 8
#define R9A07G054_CLK_M0 9
#define R9A07G054_CLK_M1 10
#define R9A07G054_CLK_M2 11
#define R9A07G054_CLK_M3 12
#define R9A07G054_CLK_M4 13
#define R9A07G054_CLK_HP 14
#define R9A07G054_CLK_TSU 15
#define R9A07G054_CLK_ZT 16
#define R9A07G054_CLK_P0 17
#define R9A07G054_CLK_P1 18
#define R9A07G054_CLK_P2 19
#define R9A07G054_CLK_AT 20
#define R9A07G054_OSCCLK 21
#define R9A07G054_CLK_P0_DIV2 22
#define R9A07G054_CLK_DRP_M 23
#define R9A07G054_CLK_DRP_D 24
#define R9A07G054_CLK_DRP_A 25
/* R9A07G054 Module Clocks */
#define R9A07G054_CA55_SCLK 0
#define R9A07G054_CA55_PCLK 1
#define R9A07G054_CA55_ATCLK 2
#define R9A07G054_CA55_GICCLK 3
#define R9A07G054_CA55_PERICLK 4
#define R9A07G054_CA55_ACLK 5
#define R9A07G054_CA55_TSCLK 6
#define R9A07G054_GIC600_GICCLK 7
#define R9A07G054_IA55_CLK 8
#define R9A07G054_IA55_PCLK 9
#define R9A07G054_MHU_PCLK 10
#define R9A07G054_SYC_CNT_CLK 11
#define R9A07G054_DMAC_ACLK 12
#define R9A07G054_DMAC_PCLK 13
#define R9A07G054_OSTM0_PCLK 14
#define R9A07G054_OSTM1_PCLK 15
#define R9A07G054_OSTM2_PCLK 16
#define R9A07G054_MTU_X_MCK_MTU3 17
#define R9A07G054_POE3_CLKM_POE 18
#define R9A07G054_GPT_PCLK 19
#define R9A07G054_POEG_A_CLKP 20
#define R9A07G054_POEG_B_CLKP 21
#define R9A07G054_POEG_C_CLKP 22
#define R9A07G054_POEG_D_CLKP 23
#define R9A07G054_WDT0_PCLK 24
#define R9A07G054_WDT0_CLK 25
#define R9A07G054_WDT1_PCLK 26
#define R9A07G054_WDT1_CLK 27
#define R9A07G054_WDT2_PCLK 28
#define R9A07G054_WDT2_CLK 29
#define R9A07G054_SPI_CLK2 30
#define R9A07G054_SPI_CLK 31
#define R9A07G054_SDHI0_IMCLK 32
#define R9A07G054_SDHI0_IMCLK2 33
#define R9A07G054_SDHI0_CLK_HS 34
#define R9A07G054_SDHI0_ACLK 35
#define R9A07G054_SDHI1_IMCLK 36
#define R9A07G054_SDHI1_IMCLK2 37
#define R9A07G054_SDHI1_CLK_HS 38
#define R9A07G054_SDHI1_ACLK 39
#define R9A07G054_GPU_CLK 40
#define R9A07G054_GPU_AXI_CLK 41
#define R9A07G054_GPU_ACE_CLK 42
#define R9A07G054_ISU_ACLK 43
#define R9A07G054_ISU_PCLK 44
#define R9A07G054_H264_CLK_A 45
#define R9A07G054_H264_CLK_P 46
#define R9A07G054_CRU_SYSCLK 47
#define R9A07G054_CRU_VCLK 48
#define R9A07G054_CRU_PCLK 49
#define R9A07G054_CRU_ACLK 50
#define R9A07G054_MIPI_DSI_PLLCLK 51
#define R9A07G054_MIPI_DSI_SYSCLK 52
#define R9A07G054_MIPI_DSI_ACLK 53
#define R9A07G054_MIPI_DSI_PCLK 54
#define R9A07G054_MIPI_DSI_VCLK 55
#define R9A07G054_MIPI_DSI_LPCLK 56
#define R9A07G054_LCDC_CLK_A 57
#define R9A07G054_LCDC_CLK_P 58
#define R9A07G054_LCDC_CLK_D 59
#define R9A07G054_SSI0_PCLK2 60
#define R9A07G054_SSI0_PCLK_SFR 61
#define R9A07G054_SSI1_PCLK2 62
#define R9A07G054_SSI1_PCLK_SFR 63
#define R9A07G054_SSI2_PCLK2 64
#define R9A07G054_SSI2_PCLK_SFR 65
#define R9A07G054_SSI3_PCLK2 66
#define R9A07G054_SSI3_PCLK_SFR 67
#define R9A07G054_SRC_CLKP 68
#define R9A07G054_USB_U2H0_HCLK 69
#define R9A07G054_USB_U2H1_HCLK 70
#define R9A07G054_USB_U2P_EXR_CPUCLK 71
#define R9A07G054_USB_PCLK 72
#define R9A07G054_ETH0_CLK_AXI 73
#define R9A07G054_ETH0_CLK_CHI 74
#define R9A07G054_ETH1_CLK_AXI 75
#define R9A07G054_ETH1_CLK_CHI 76
#define R9A07G054_I2C0_PCLK 77
#define R9A07G054_I2C1_PCLK 78
#define R9A07G054_I2C2_PCLK 79
#define R9A07G054_I2C3_PCLK 80
#define R9A07G054_SCIF0_CLK_PCK 81
#define R9A07G054_SCIF1_CLK_PCK 82
#define R9A07G054_SCIF2_CLK_PCK 83
#define R9A07G054_SCIF3_CLK_PCK 84
#define R9A07G054_SCIF4_CLK_PCK 85
#define R9A07G054_SCI0_CLKP 86
#define R9A07G054_SCI1_CLKP 87
#define R9A07G054_IRDA_CLKP 88
#define R9A07G054_RSPI0_CLKB 89
#define R9A07G054_RSPI1_CLKB 90
#define R9A07G054_RSPI2_CLKB 91
#define R9A07G054_CANFD_PCLK 92
#define R9A07G054_GPIO_HCLK 93
#define R9A07G054_ADC_ADCLK 94
#define R9A07G054_ADC_PCLK 95
#define R9A07G054_TSU_PCLK 96
#define R9A07G054_STPAI_INITCLK 97
#define R9A07G054_STPAI_ACLK 98
#define R9A07G054_STPAI_MCLK 99
#define R9A07G054_STPAI_DCLKIN 100
#define R9A07G054_STPAI_ACLK_DRP 101
/* R9A07G054 Resets */
#define R9A07G054_CA55_RST_1_0 0
#define R9A07G054_CA55_RST_1_1 1
#define R9A07G054_CA55_RST_3_0 2
#define R9A07G054_CA55_RST_3_1 3
#define R9A07G054_CA55_RST_4 4
#define R9A07G054_CA55_RST_5 5
#define R9A07G054_CA55_RST_6 6
#define R9A07G054_CA55_RST_7 7
#define R9A07G054_CA55_RST_8 8
#define R9A07G054_CA55_RST_9 9
#define R9A07G054_CA55_RST_10 10
#define R9A07G054_CA55_RST_11 11
#define R9A07G054_CA55_RST_12 12
#define R9A07G054_GIC600_GICRESET_N 13
#define R9A07G054_GIC600_DBG_GICRESET_N 14
#define R9A07G054_IA55_RESETN 15
#define R9A07G054_MHU_RESETN 16
#define R9A07G054_DMAC_ARESETN 17
#define R9A07G054_DMAC_RST_ASYNC 18
#define R9A07G054_SYC_RESETN 19
#define R9A07G054_OSTM0_PRESETZ 20
#define R9A07G054_OSTM1_PRESETZ 21
#define R9A07G054_OSTM2_PRESETZ 22
#define R9A07G054_MTU_X_PRESET_MTU3 23
#define R9A07G054_POE3_RST_M_REG 24
#define R9A07G054_GPT_RST_C 25
#define R9A07G054_POEG_A_RST 26
#define R9A07G054_POEG_B_RST 27
#define R9A07G054_POEG_C_RST 28
#define R9A07G054_POEG_D_RST 29
#define R9A07G054_WDT0_PRESETN 30
#define R9A07G054_WDT1_PRESETN 31
#define R9A07G054_WDT2_PRESETN 32
#define R9A07G054_SPI_RST 33
#define R9A07G054_SDHI0_IXRST 34
#define R9A07G054_SDHI1_IXRST 35
#define R9A07G054_GPU_RESETN 36
#define R9A07G054_GPU_AXI_RESETN 37
#define R9A07G054_GPU_ACE_RESETN 38
#define R9A07G054_ISU_ARESETN 39
#define R9A07G054_ISU_PRESETN 40
#define R9A07G054_H264_X_RESET_VCP 41
#define R9A07G054_H264_CP_PRESET_P 42
#define R9A07G054_CRU_CMN_RSTB 43
#define R9A07G054_CRU_PRESETN 44
#define R9A07G054_CRU_ARESETN 45
#define R9A07G054_MIPI_DSI_CMN_RSTB 46
#define R9A07G054_MIPI_DSI_ARESET_N 47
#define R9A07G054_MIPI_DSI_PRESET_N 48
#define R9A07G054_LCDC_RESET_N 49
#define R9A07G054_SSI0_RST_M2_REG 50
#define R9A07G054_SSI1_RST_M2_REG 51
#define R9A07G054_SSI2_RST_M2_REG 52
#define R9A07G054_SSI3_RST_M2_REG 53
#define R9A07G054_SRC_RST 54
#define R9A07G054_USB_U2H0_HRESETN 55
#define R9A07G054_USB_U2H1_HRESETN 56
#define R9A07G054_USB_U2P_EXL_SYSRST 57
#define R9A07G054_USB_PRESETN 58
#define R9A07G054_ETH0_RST_HW_N 59
#define R9A07G054_ETH1_RST_HW_N 60
#define R9A07G054_I2C0_MRST 61
#define R9A07G054_I2C1_MRST 62
#define R9A07G054_I2C2_MRST 63
#define R9A07G054_I2C3_MRST 64
#define R9A07G054_SCIF0_RST_SYSTEM_N 65
#define R9A07G054_SCIF1_RST_SYSTEM_N 66
#define R9A07G054_SCIF2_RST_SYSTEM_N 67
#define R9A07G054_SCIF3_RST_SYSTEM_N 68
#define R9A07G054_SCIF4_RST_SYSTEM_N 69
#define R9A07G054_SCI0_RST 70
#define R9A07G054_SCI1_RST 71
#define R9A07G054_IRDA_RST 72
#define R9A07G054_RSPI0_RST 73
#define R9A07G054_RSPI1_RST 74
#define R9A07G054_RSPI2_RST 75
#define R9A07G054_CANFD_RSTP_N 76
#define R9A07G054_CANFD_RSTC_N 77
#define R9A07G054_GPIO_RSTN 78
#define R9A07G054_GPIO_PORT_RESETN 79
#define R9A07G054_GPIO_SPARE_RESETN 80
#define R9A07G054_ADC_PRESETN 81
#define R9A07G054_ADC_ADRST_N 82
#define R9A07G054_TSU_PRESETN 83
#define R9A07G054_STPAI_ARESETN 84
#endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */