clk: samsung: Add clock IDs for the CMU_CDREX (DRAM Express Controller)
This patch adds missing clock IDs for CMU_CDREX (DRAM Express Controller) which generates clocks for DRAM and NoC (Network on Chip) busses. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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@ -214,6 +214,9 @@
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#define CLK_MOUT_SW_ACLK400 651
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#define CLK_MOUT_USER_ACLK300_GSCL 652
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#define CLK_MOUT_SW_ACLK300_GSCL 653
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#define CLK_MOUT_MCLK_CDREX 654
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#define CLK_MOUT_BPLL 655
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#define CLK_MOUT_MX_MSPLL_CCORE 656
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/* divider clocks */
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#define CLK_DOUT_PIXEL 768
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@ -239,8 +242,14 @@
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#define CLK_DOUT_ACLK300_DISP1 788
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#define CLK_DOUT_ACLK300_GSCL 789
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#define CLK_DOUT_ACLK400_DISP1 790
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#define CLK_DOUT_PCLK_CDREX 791
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#define CLK_DOUT_SCLK_CDREX 792
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#define CLK_DOUT_ACLK_CDREX1 793
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#define CLK_DOUT_CCLK_DREX0 794
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#define CLK_DOUT_CLK2X_PHY0 795
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#define CLK_DOUT_PCLK_CORE_MEM 796
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/* must be greater than maximal clock id */
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#define CLK_NR_CLKS 791
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#define CLK_NR_CLKS 797
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
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