ASoC: rsnd: add rsnd_dvc_initialize_lock/unlock()
Renesas SCU (Sampling Rate Convert Unit) includes SRC/CTU/MIX/DVC, and these have similar register. xxxIR (Initialization Register) is one of them. These xxxIR need be set to 1 during initialization. Current rsnd driver has src.c / dvc.c, and we will have mix.c. It is readable if these have same named function. This patch adds rsnd_dvc_initialize_lock/unlock() and make sure it Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -70,6 +70,13 @@ static void rsnd_dvc_soft_reset(struct rsnd_mod *mod)
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rsnd_mod_write(mod, DVC_SWRSR, 1);
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}
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#define rsnd_dvc_initialize_lock(mod) __rsnd_dvc_initialize_lock(mod, 1)
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#define rsnd_dvc_initialize_unlock(mod) __rsnd_dvc_initialize_lock(mod, 0)
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static void __rsnd_dvc_initialize_lock(struct rsnd_mod *mod, u32 enable)
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{
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rsnd_mod_write(mod, DVC_DVUIR, enable);
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}
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static void rsnd_dvc_volume_update(struct rsnd_dai_stream *io,
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struct rsnd_mod *mod)
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{
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@ -150,17 +157,15 @@ static int rsnd_dvc_init(struct rsnd_mod *mod,
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rsnd_dvc_soft_reset(mod);
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rsnd_path_parse(priv, io);
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rsnd_dvc_initialize_lock(mod);
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rsnd_mod_write(mod, DVC_DVUIR, 1);
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rsnd_path_parse(priv, io);
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rsnd_mod_write(mod, DVC_ADINR, rsnd_get_adinr(mod, io));
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/* ch0/ch1 Volume */
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rsnd_dvc_volume_update(io, mod);
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rsnd_mod_write(mod, DVC_DVUIR, 0);
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rsnd_adg_set_cmd_timsel_gen2(mod, io);
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return 0;
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@ -179,6 +184,8 @@ static int rsnd_dvc_start(struct rsnd_mod *mod,
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struct rsnd_dai_stream *io,
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struct rsnd_priv *priv)
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{
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rsnd_dvc_initialize_unlock(mod);
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rsnd_mod_write(mod, CMD_CTRL, 0x10);
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return 0;
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