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ARM: dts: r7s72100: update sdhi clock bindings 

The SDHI controller in the RZ/A1 has 2 clock sources per channel and both
need to be enabled/disabled for proper operation. This fixes the fact that
the define for R7S72100_CLK_SDHI1 was not correct to begin with (typo), and
that all 4 clock sources need to be defined an used.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Chris Brandt 2017-01-25 15:28:10 -05:00 committed by Simon Horman
parent c1ae3cfa0e
commit 3d2abda02a
2 changed files with 16 additions and 7 deletions
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17
arch/arm/boot/dts/r7s72100.dtsi
View File

@ -162,9 +162,12 @@ mstp12_clks: mstp12_clks@fcfe0444 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0444 4>;
clocks = <&p1_clk>, <&p1_clk>;
clock-indices = <R7S72100_CLK_SDHI1 R7S72100_CLK_SDHI0>;
clock-output-names = "sdhi1", "sdhi0";
clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
clock-indices = <
R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
>;
clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
};
};
@ -488,7 +491,9 @@ sdhi0: sd@e804e000 {
GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp12_clks R7S72100_CLK_SDHI0>;
clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
<&mstp12_clks R7S72100_CLK_SDHI01>;
clock-names = "core", "cd";
cap-sd-highspeed;
cap-sdio-irq;
status = "disabled";
@ -501,7 +506,9 @@ sdhi1: sd@e804e800 {
GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp12_clks R7S72100_CLK_SDHI1>;
clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
<&mstp12_clks R7S72100_CLK_SDHI11>;
clock-names = "core", "cd";
cap-sd-highspeed;
cap-sdio-irq;
status = "disabled";

6
include/dt-bindings/clock/r7s72100-clock.h
View File

@ -49,7 +49,9 @@
#define R7S72100_CLK_SPI4 3
/* MSTP12 */
#define R7S72100_CLK_SDHI0 3
#define R7S72100_CLK_SDHI1 2
#define R7S72100_CLK_SDHI00 3
#define R7S72100_CLK_SDHI01 2
#define R7S72100_CLK_SDHI10 1
#define R7S72100_CLK_SDHI11 0
#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */