perf vendor events arm64: add HiSilicon hip08 JSON file
This patch adds the HiSilicon hip08 JSON file. This platform follows the ARMv8 recommended IMPLEMENTATION DEFINED events, where applicable. Signed-off-by: John Garry <john.garry@huawei.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Shaokun Zhang <zhangshaokun@hisilicon.com> Cc: Will Deacon <will.deacon@arm.com> Cc: William Cohen <wcohen@redhat.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linuxarm@huawei.com Link: http://lkml.kernel.org/r/1520506716-197429-12-git-send-email-john.garry@huawei.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
John Garry
Arnaldo Carvalho de Melo
parent
afe4d08962
commit
3d4caec160
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[
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{
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"ArchStdEvent": "L1D_CACHE_RD",
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},
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{
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"ArchStdEvent": "L1D_CACHE_WR",
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},
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{
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"ArchStdEvent": "L1D_CACHE_REFILL_RD",
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},
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{
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"ArchStdEvent": "L1D_CACHE_REFILL_WR",
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},
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{
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"ArchStdEvent": "L1D_CACHE_WB_VICTIM",
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},
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{
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"ArchStdEvent": "L1D_CACHE_WB_CLEAN",
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},
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{
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"ArchStdEvent": "L1D_CACHE_INVAL",
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},
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{
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"ArchStdEvent": "L1D_TLB_REFILL_RD",
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},
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{
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"ArchStdEvent": "L1D_TLB_REFILL_WR",
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},
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{
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"ArchStdEvent": "L1D_TLB_RD",
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},
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{
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"ArchStdEvent": "L1D_TLB_WR",
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},
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{
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"ArchStdEvent": "L2D_CACHE_RD",
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},
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{
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"ArchStdEvent": "L2D_CACHE_WR",
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},
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{
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"ArchStdEvent": "L2D_CACHE_REFILL_RD",
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},
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{
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"ArchStdEvent": "L2D_CACHE_REFILL_WR",
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},
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{
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"ArchStdEvent": "L2D_CACHE_WB_VICTIM",
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},
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{
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"ArchStdEvent": "L2D_CACHE_WB_CLEAN",
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},
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{
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"ArchStdEvent": "L2D_CACHE_INVAL",
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},
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{
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"PublicDescription": "Level 1 instruction cache prefetch access count",
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"EventCode": "0x102e",
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"EventName": "L1I_CACHE_PRF",
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"BriefDescription": "L1I cache prefetch access count",
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},
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{
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"PublicDescription": "Level 1 instruction cache miss due to prefetch access count",
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"EventCode": "0x102f",
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"EventName": "L1I_CACHE_PRF_REFILL",
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"BriefDescription": "L1I cache miss due to prefetch access count",
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},
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{
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"PublicDescription": "Instruction queue is empty",
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"EventCode": "0x1043",
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"EventName": "IQ_IS_EMPTY",
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"BriefDescription": "Instruction queue is empty",
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},
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{
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"PublicDescription": "Instruction fetch stall cycles",
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"EventCode": "0x1044",
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"EventName": "IF_IS_STALL",
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"BriefDescription": "Instruction fetch stall cycles",
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},
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{
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"PublicDescription": "Instructions can receive, but not send",
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"EventCode": "0x2014",
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"EventName": "FETCH_BUBBLE",
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"BriefDescription": "Instructions can receive, but not send",
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},
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{
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"PublicDescription": "Prefetch request from LSU",
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"EventCode": "0x6013",
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"EventName": "PRF_REQ",
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"BriefDescription": "Prefetch request from LSU",
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},
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{
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"PublicDescription": "Hit on prefetched data",
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"EventCode": "0x6014",
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"EventName": "HIT_ON_PRF",
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"BriefDescription": "Hit on prefetched data",
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},
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{
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"PublicDescription": "Cycles of that the number of issuing micro operations are less than 4",
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"EventCode": "0x7001",
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"EventName": "EXE_STALL_CYCLE",
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"BriefDescription": "Cycles of that the number of issue ups are less than 4",
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},
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{
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"PublicDescription": "No any micro operation is issued and meanwhile any load operation is not resolved",
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"EventCode": "0x7004",
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"EventName": "MEM_STALL_ANYLOAD",
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"BriefDescription": "No any micro operation is issued and meanwhile any load operation is not resolved",
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},
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{
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"PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill",
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"EventCode": "0x7006",
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"EventName": "MEM_STALL_L1MISS",
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"BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill",
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},
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{
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"PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache",
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"EventCode": "0x7007",
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"EventName": "MEM_STALL_L2MISS",
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"BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache",
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},
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]
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@ -14,3 +14,4 @@
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#Family-model,Version,Filename,EventType
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#Family-model,Version,Filename,EventType
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0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core
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0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core
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0x00000000420f5160,v1,cavium/thunderx2,core
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0x00000000420f5160,v1,cavium/thunderx2,core
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0x00000000480fd010,v1,hisilicon/hip08,core
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