p71924506
/
linux_old1
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

clk: tegra: Fix pllx dyn step calculation 

The logic for calculating the input rate used when figuring out the
proper dynamic steps for pllx was incorrect. It is supposed to be
calculated using parent_rate / m but it was just using the parent rate
directly, therefore using the wrong step values.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Rhyland Klein 2016-01-14 14:24:35 -05:00 committed by Thierry Reding
parent 3eb61566a6
commit 3dad5c5fa1
1 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/clk/tegra/clk-tegra210.c
View File

@ -780,13 +780,13 @@ static void pllx_get_dyn_steps(struct clk_hw *hw, u32 *step_a, u32 *step_b)
{
unsigned long input_rate;
if (!IS_ERR_OR_NULL(hw->clk)) {
/* cf rate */
if (!IS_ERR_OR_NULL(hw->clk))
input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
/* cf rate */
input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate);
} else {
else
input_rate = 38400000;
}
input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate);
switch (input_rate) {
case 12000000: