ARM: shmobile: r8a7794: Add SGX clock to device tree
Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -461,16 +461,15 @@ mstp0_clks: mstp0_clks@e6150130 {
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mstp1_clks: mstp1_clks@e6150134 {
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compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
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clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
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<&cp_clk>,
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<&zs_clk>, <&zs_clk>, <&zs_clk>;
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clocks = <&p_clk>, <&zg_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
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<&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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R8A7794_CLK_TMU1 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2
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R8A7794_CLK_CMT0 R8A7794_CLK_TMU0
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R8A7794_CLK_TMU1 R8A7794_CLK_3DG R8A7794_CLK_TMU3
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R8A7794_CLK_TMU2 R8A7794_CLK_CMT0 R8A7794_CLK_TMU0
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>;
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clock-output-names =
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"tmu1", "tmu3", "tmu2", "cmt0", "tmu0";
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"tmu1", "3dg", "tmu3", "tmu2", "cmt0", "tmu0";
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};
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mstp2_clks: mstp2_clks@e6150138 {
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compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
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@ -27,6 +27,7 @@
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/* MSTP1 */
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#define R8A7794_CLK_TMU1 11
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#define R8A7794_CLK_3DG 12
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#define R8A7794_CLK_TMU3 21
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#define R8A7794_CLK_TMU2 22
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#define R8A7794_CLK_CMT0 24
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