Merge branch 'pci/aspm' into next
* pci/aspm: PCI/ASPM: Unexport internal ASPM interfaces PCI/ASPM: Enable Latency Tolerance Reporting when supported PCI/ASPM: Calculate LTR_L1.2_THRESHOLD from device characteristics
This commit is contained in:
Bjorn Helgaas
Bjorn Helgaas
commit
3ea8bc3326
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@ -342,6 +342,26 @@ static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
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void pci_enable_acs(struct pci_dev *dev);
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#ifdef CONFIG_PCIEASPM
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void pcie_aspm_init_link_state(struct pci_dev *pdev);
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void pcie_aspm_exit_link_state(struct pci_dev *pdev);
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void pcie_aspm_pm_state_change(struct pci_dev *pdev);
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void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
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#else
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static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
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static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
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static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
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static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
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#endif
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#ifdef CONFIG_PCIEASPM_DEBUG
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void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev);
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void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev);
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#else
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static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) { }
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static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) { }
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#endif
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#ifdef CONFIG_PCIE_PTM
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void pci_ptm_init(struct pci_dev *dev);
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#else
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@ -43,18 +43,6 @@
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#define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1 | \
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ASPM_STATE_L1SS)
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/*
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* When L1 substates are enabled, the LTR L1.2 threshold is a timing parameter
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* that decides whether L1.1 or L1.2 is entered (Refer PCIe spec for details).
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* Not sure is there is a way to "calculate" this on the fly, but maybe we
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* could turn it into a parameter in future. This value has been taken from
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* the following files from Intel's coreboot (which is the only code I found
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* to have used this):
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* https://www.coreboot.org/pipermail/coreboot-gerrit/2015-March/021134.html
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* https://review.coreboot.org/#/c/8832/
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*/
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#define LTR_L1_2_THRESHOLD_BITS ((1 << 21) | (1 << 23) | (1 << 30))
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struct aspm_latency {
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u32 l0s; /* L0s latency (nsec) */
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u32 l1; /* L1 latency (nsec) */
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@ -333,6 +321,32 @@ static u32 calc_l1ss_pwron(struct pci_dev *pdev, u32 scale, u32 val)
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return 0;
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}
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static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
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{
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u64 threshold_ns = threshold_us * 1000;
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/* See PCIe r3.1, sec 7.33.3 and sec 6.18 */
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if (threshold_ns < 32) {
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*scale = 0;
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*value = threshold_ns;
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} else if (threshold_ns < 1024) {
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*scale = 1;
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*value = threshold_ns >> 5;
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} else if (threshold_ns < 32768) {
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*scale = 2;
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*value = threshold_ns >> 10;
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} else if (threshold_ns < 1048576) {
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*scale = 3;
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*value = threshold_ns >> 15;
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} else if (threshold_ns < 33554432) {
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*scale = 4;
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*value = threshold_ns >> 20;
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} else {
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*scale = 5;
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*value = threshold_ns >> 25;
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}
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}
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struct aspm_register_info {
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u32 support:2;
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u32 enabled:2;
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@ -443,6 +457,7 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link,
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struct aspm_register_info *dwreg)
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{
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u32 val1, val2, scale1, scale2;
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u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
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link->l1ss.up_cap_ptr = upreg->l1ss_cap_ptr;
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link->l1ss.dw_cap_ptr = dwreg->l1ss_cap_ptr;
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@ -454,16 +469,7 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link,
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/* Choose the greater of the two Port Common_Mode_Restore_Times */
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val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
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val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
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if (val1 > val2)
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link->l1ss.ctl1 |= val1 << 8;
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else
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link->l1ss.ctl1 |= val2 << 8;
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/*
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* We currently use LTR L1.2 threshold to be fixed constant picked from
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* Intel's coreboot.
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*/
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link->l1ss.ctl1 |= LTR_L1_2_THRESHOLD_BITS;
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t_common_mode = max(val1, val2);
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/* Choose the greater of the two Port T_POWER_ON times */
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val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
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@ -472,10 +478,27 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link,
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scale2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
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if (calc_l1ss_pwron(link->pdev, scale1, val1) >
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calc_l1ss_pwron(link->downstream, scale2, val2))
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calc_l1ss_pwron(link->downstream, scale2, val2)) {
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link->l1ss.ctl2 |= scale1 | (val1 << 3);
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else
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t_power_on = calc_l1ss_pwron(link->pdev, scale1, val1);
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} else {
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link->l1ss.ctl2 |= scale2 | (val2 << 3);
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t_power_on = calc_l1ss_pwron(link->downstream, scale2, val2);
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}
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/*
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* Set LTR_L1.2_THRESHOLD to the time required to transition the
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* Link from L0 to L1.2 and back to L0 so we enter L1.2 only if
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* downstream devices report (via LTR) that they can tolerate at
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* least that much latency.
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*
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* Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and
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* Table 5-11. T(POWER_OFF) is at most 2us and T(L1.2) is at
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* least 4us.
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*/
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l1_2_threshold = 2 + 4 + t_common_mode + t_power_on;
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encode_l12_threshold(l1_2_threshold, &scale, &value);
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link->l1ss.ctl1 |= t_common_mode << 8 | scale << 29 | value << 16;
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}
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static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
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@ -1875,6 +1875,38 @@ static void pci_configure_relaxed_ordering(struct pci_dev *dev)
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}
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}
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static void pci_configure_ltr(struct pci_dev *dev)
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{
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#ifdef CONFIG_PCIEASPM
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u32 cap;
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struct pci_dev *bridge;
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if (!pci_is_pcie(dev))
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return;
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pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
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if (!(cap & PCI_EXP_DEVCAP2_LTR))
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return;
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/*
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* Software must not enable LTR in an Endpoint unless the Root
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* Complex and all intermediate Switches indicate support for LTR.
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* PCIe r3.1, sec 6.18.
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*/
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if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
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dev->ltr_path = 1;
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else {
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bridge = pci_upstream_bridge(dev);
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if (bridge && bridge->ltr_path)
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dev->ltr_path = 1;
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}
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if (dev->ltr_path)
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pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
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PCI_EXP_DEVCTL2_LTR_EN);
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#endif
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}
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static void pci_configure_device(struct pci_dev *dev)
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{
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struct hotplug_params hpp;
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@ -1883,6 +1915,7 @@ static void pci_configure_device(struct pci_dev *dev)
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pci_configure_mps(dev);
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pci_configure_extended_tags(dev, NULL);
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pci_configure_relaxed_ordering(dev);
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pci_configure_ltr(dev);
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memset(&hpp, 0, sizeof(hpp));
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ret = pci_get_hp_params(dev, &hpp);
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@ -24,43 +24,12 @@
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#define PCIE_LINK_STATE_CLKPM 4
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#ifdef CONFIG_PCIEASPM
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void pcie_aspm_init_link_state(struct pci_dev *pdev);
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void pcie_aspm_exit_link_state(struct pci_dev *pdev);
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void pcie_aspm_pm_state_change(struct pci_dev *pdev);
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void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
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void pci_disable_link_state(struct pci_dev *pdev, int state);
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void pci_disable_link_state_locked(struct pci_dev *pdev, int state);
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void pcie_no_aspm(void);
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#else
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static inline void pcie_aspm_init_link_state(struct pci_dev *pdev)
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{
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}
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static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev)
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{
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}
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static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev)
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{
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}
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static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
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{
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}
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static inline void pci_disable_link_state(struct pci_dev *pdev, int state)
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{
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}
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static inline void pcie_no_aspm(void)
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{
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}
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static inline void pci_disable_link_state(struct pci_dev *pdev, int state) { }
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static inline void pcie_no_aspm(void) { }
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#endif
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#ifdef CONFIG_PCIEASPM_DEBUG /* this depends on CONFIG_PCIEASPM */
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void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev);
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void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev);
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#else
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static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
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{
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}
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static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
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{
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}
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#endif
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#endif /* LINUX_ASPM_H */
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@ -350,6 +350,8 @@ struct pci_dev {
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#ifdef CONFIG_PCIEASPM
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struct pcie_link_state *link_state; /* ASPM link state */
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unsigned int ltr_path:1; /* Latency Tolerance Reporting
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supported from root to here */
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#endif
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pci_channel_state_t error_state; /* current connectivity state */
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