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ARM: tegra: Devicetree changes for v4.4-rc1 

Mostly a bunch of updates to the Toradex Apalis and Colibri platforms
 along with a couple of cleanup patches.
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Merge tag 'tegra-for-4.4-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt

ARM: tegra: Devicetree changes for v4.4-rc1

Mostly a bunch of updates to the Toradex Apalis and Colibri platforms
along with a couple of cleanup patches.

* tag 'tegra-for-4.4-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (25 commits)
  ARM: tegra: Use consistent indentation for SATA node
  ARM: tegra: colibri-eval: Fix power/wakeup key
  ARM: tegra: colibri-eval: Add comment concerning SD/MMC
  ARM: tegra: colibri-eval: Fix vendor string of M41T0M6 RTC
  ARM: tegra: colibri: Properly align pin names
  ARM: tegra: colibri: Replace eMMC label by comment
  ARM: tegra: colibri: Activate STMPE811 touch controller
  ARM: tegra: colibri: Add touch pen interrupt pin muxing
  ARM: tegra: colibri: Fix comment about 3v3 fixed supply
  ARM: tegra: colibri: Add pin muxing for on-module power I2C
  ARM: tegra: colibri: Improve comment about thermal alert pin
  ARM: tegra: colibri: Fix HDMI supplies
  ARM: tegra: colibri: Update hardware revisions compatibility
  ARM: tegra: apalis-eval: Fix power/wakeup key
  ARM: tegra: apalis-eval: Fix backlight PWM comment
  ARM: tegra: apalis-eval: Set OTG dr_mode
  ARM: tegra: apalis-eval: Enable HDA controller
  ARM: tegra: apalis: Properly align pin names
  ARM: tegra: apalis: Add digital audio pin muxing
  ARM: tegra: apalis: Add comment concerning eMMC
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2015-10-26 09:53:14 +09:00
parent 41adfe8202 481b4f1a3f
commit 3eb52a06d5
8 changed files with 315 additions and 166 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
arch/arm/boot/dts/tegra124-nyan.dtsi
View File

@ -159,7 +159,7 @@ regulators {
vin-ldo9-10-supply = <&vdd_5v0_sys>;
vin-ldo11-supply = <&vdd_3v3_run>;
sd0 {
vdd_cpu: sd0 {
regulator-name = "+VDD_CPU_AP";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
@ -397,6 +397,13 @@ sdhci@0,700b0600 { /* eMMC on this bus */
non-removable;
};
/* CPU DFLL clock */
clock@0,70110000 {
status = "okay";
vdd-cpu-supply = <&vdd_cpu>;
nvidia,i2c-fs-rate = <400000>;
};
ahub@0,70300000 {
i2s@0,70301100 {
status = "okay";
@ -487,6 +494,12 @@ clk32k_in: clock@0 {
};
};
cpus {
cpu@0 {
vdd-cpu-supply = <&vdd_cpu>;
};
};
gpio-keys {
compatible = "gpio-keys";

20
arch/arm/boot/dts/tegra124.dtsi
View File

@ -608,26 +608,20 @@ emc: emc@0,7001b000 {
sata@0,70020000 {
compatible = "nvidia,tegra124-ahci";
reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
<0x0 0x70020000 0x0 0x7000>; /* SATA */
<0x0 0x70020000 0x0 0x7000>; /* SATA */
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_SATA>,
<&tegra_car TEGRA124_CLK_SATA_OOB>,
<&tegra_car TEGRA124_CLK_CML1>,
<&tegra_car TEGRA124_CLK_PLL_E>;
<&tegra_car TEGRA124_CLK_SATA_OOB>,
<&tegra_car TEGRA124_CLK_CML1>,
<&tegra_car TEGRA124_CLK_PLL_E>;
clock-names = "sata", "sata-oob", "cml1", "pll_e";
resets = <&tegra_car 124>,
<&tegra_car 123>,
<&tegra_car 129>;
<&tegra_car 123>,
<&tegra_car 129>;
reset-names = "sata", "sata-oob", "sata-cold";
phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
phy-names = "sata-phy";
status = "disabled";
};
@ -636,7 +630,7 @@ hda@0,70030000 {
reg = <0x0 0x70030000 0x0 0x10000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_HDA>,
<&tegra_car TEGRA124_CLK_HDA2HDMI>,
<&tegra_car TEGRA124_CLK_HDA2HDMI>,
<&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
clock-names = "hda", "hda2hdmi", "hda2codec_2x";
resets = <&tegra_car 125>, /* hda */

4
arch/arm/boot/dts/tegra20.dtsi
View File

@ -601,8 +601,8 @@ pcie-controller@80003000 {
<&tegra_car TEGRA20_CLK_PLL_E>;
clock-names = "pex", "afi", "pll_e";
resets = <&tegra_car 70>,
<&tegra_car 72>,
<&tegra_car 74>;
<&tegra_car 72>,
<&tegra_car 74>;
reset-names = "pex", "afi", "pcie_x";
status = "disabled";

13
arch/arm/boot/dts/tegra30-apalis-eval.dts
View File

@ -126,6 +126,10 @@ spidev1: spidev@2 {
};
};
hda@70030000 {
status = "okay";
};
sd1: sdhci@78000000 {
status = "okay";
bus-width = <4>;
@ -149,6 +153,7 @@ usb@7d000000 {
usb-phy@7d000000 {
status = "okay";
dr_mode = "otg";
vbus-supply = <&usbo1_vbus_reg>;
};
@ -175,7 +180,7 @@ usb-phy@7d008000 {
backlight: backlight {
compatible = "pwm-backlight";
/* PWM0 */
/* PWM_BKL1 */
pwms = <&pwm 0 5000000>;
brightness-levels = <255 231 223 207 191 159 127 0>;
default-brightness-level = <6>;
@ -186,10 +191,10 @@ backlight: backlight {
gpio-keys {
compatible = "gpio-keys";
power {
label = "Power";
wakeup {
label = "WAKE1_MICO";
gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
linux,code = <KEY_WAKEUP>;
debounce-interval = <10>;
gpio-key,wakeup;
};

214
arch/arm/boot/dts/tegra30-apalis.dtsi
View File

@ -1,8 +1,9 @@
#include "tegra30.dtsi"
/*
* Toradex Apalis T30 Device Tree
* Compatible for Revisions 1GB: V1.0A; 2GB: V1.0B, V1.0C
* Toradex Apalis T30 Module Device Tree
* Compatible for Revisions 1GB: V1.0A, V1.1A; 1GB IT: V1.1A;
* 2GB: V1.0B, V1.0C, V1.0E, V1.1A
*/
/ {
model = "Toradex Apalis T30";
@ -33,8 +34,8 @@ pci@3,0 {
host1x@50000000 {
hdmi@54280000 {
vdd-supply = <&sys_3v3_reg>;
pll-supply = <&vio_reg>;
vdd-supply = <&avdd_hdmi_3v3_reg>;
pll-supply = <&avdd_hdmi_pll_1v8_reg>;
nvidia,hpd-gpio =
<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
@ -57,25 +58,25 @@ pv2 {
/* Apalis BKL1_PWM */
uart3_rts_n_pc0 {
nvidia,pins = "uart3_rts_n_pc0";
nvidia,pins = "uart3_rts_n_pc0";
nvidia,function = "pwm0";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
/* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */
uart3_cts_n_pa1 {
nvidia,pins = "uart3_cts_n_pa1";
nvidia,function = "rsvd1";
nvidia,pins = "uart3_cts_n_pa1";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
/* Apalis CAN1 on SPI6 */
spi2_cs0_n_px3 {
nvidia,pins = "spi2_cs0_n_px3",
"spi2_miso_px1",
"spi2_mosi_px0",
"spi2_sck_px2";
nvidia,pins = "spi2_cs0_n_px3",
"spi2_miso_px1",
"spi2_mosi_px0",
"spi2_sck_px2";
nvidia,function = "spi6";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@ -91,10 +92,10 @@ spi2_cs1_n_pw2 {
/* Apalis CAN2 on SPI4 */
gmi_a16_pj7 {
nvidia,pins = "gmi_a16_pj7",
"gmi_a17_pb0",
"gmi_a18_pb1",
"gmi_a19_pk7";
nvidia,pins = "gmi_a16_pj7",
"gmi_a17_pb0",
"gmi_a18_pb1",
"gmi_a19_pk7";
nvidia,function = "spi4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@ -108,6 +109,30 @@ spi2_cs2_n_pw3 {
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
/* Apalis Digital Audio */
clk1_req_pee2 {
nvidia,pins = "clk1_req_pee2";
nvidia,function = "hda";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
clk2_out_pw5 {
nvidia,pins = "clk2_out_pw5";
nvidia,function = "extperiph2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
dap1_fs_pn0 {
nvidia,pins = "dap1_fs_pn0",
"dap1_din_pn1",
"dap1_dout_pn2",
"dap1_sclk_pn3";
nvidia,function = "hda";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
/* Apalis I2C3 */
cam_i2c_scl_pbb1 {
nvidia,pins = "cam_i2c_scl_pbb1",
@ -122,21 +147,21 @@ cam_i2c_scl_pbb1 {
/* Apalis MMC1 */
sdmmc3_clk_pa6 {
nvidia,pins = "sdmmc3_clk_pa6",
"sdmmc3_cmd_pa7";
nvidia,pins = "sdmmc3_clk_pa6",
"sdmmc3_cmd_pa7";
nvidia,function = "sdmmc3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
sdmmc3_dat0_pb7 {
nvidia,pins = "sdmmc3_dat0_pb7",
"sdmmc3_dat1_pb6",
"sdmmc3_dat2_pb5",
"sdmmc3_dat3_pb4",
"sdmmc3_dat4_pd1",
"sdmmc3_dat5_pd0",
"sdmmc3_dat6_pd3",
"sdmmc3_dat7_pd4";
nvidia,pins = "sdmmc3_dat0_pb7",
"sdmmc3_dat1_pb6",
"sdmmc3_dat2_pb5",
"sdmmc3_dat3_pb4",
"sdmmc3_dat4_pd1",
"sdmmc3_dat5_pd0",
"sdmmc3_dat6_pd3",
"sdmmc3_dat7_pd4";
nvidia,function = "sdmmc3";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@ -151,32 +176,32 @@ pv3 {
};
/* Apalis PWM1 */
gpio_pu6 {
nvidia,pins = "gpio_pu6";
pu6 {
nvidia,pins = "pu6";
nvidia,function = "pwm3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
/* Apalis PWM2 */
gpio_pu5 {
nvidia,pins = "gpio_pu5";
pu5 {
nvidia,pins = "pu5";
nvidia,function = "pwm2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
/* Apalis PWM3 */
gpio_pu4 {
nvidia,pins = "gpio_pu4";
pu4 {
nvidia,pins = "pu4";
nvidia,function = "pwm1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
/* Apalis PWM4 */
gpio_pu3 {
nvidia,pins = "gpio_pu3";
pu3 {
nvidia,pins = "pu3";
nvidia,function = "pwm0";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@ -198,11 +223,11 @@ sdmmc1_clk_pz0 {
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
sdmmc1_cmd_pz1 {
nvidia,pins = "sdmmc1_cmd_pz1",
"sdmmc1_dat0_py7",
"sdmmc1_dat1_py6",
"sdmmc1_dat2_py5",
"sdmmc1_dat3_py4";
nvidia,pins = "sdmmc1_cmd_pz1",
"sdmmc1_dat0_py7",
"sdmmc1_dat1_py6",
"sdmmc1_dat2_py5",
"sdmmc1_dat3_py4";
nvidia,function = "sdmmc1";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@ -218,10 +243,10 @@ clk2_req_pcc5 {
/* Apalis SPI1 */
spi1_sck_px5 {
nvidia,pins = "spi1_sck_px5",
"spi1_mosi_px4",
"spi1_miso_px7",
"spi1_cs0_n_px6";
nvidia,pins = "spi1_sck_px5",
"spi1_mosi_px4",
"spi1_miso_px7",
"spi1_cs0_n_px6";
nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@ -229,10 +254,10 @@ spi1_sck_px5 {
/* Apalis SPI2 */
lcd_sck_pz4 {
nvidia,pins = "lcd_sck_pz4",
"lcd_sdout_pn5",
"lcd_sdin_pz2",
"lcd_cs0_n_pn4";
nvidia,pins = "lcd_sck_pz4",
"lcd_sdout_pn5",
"lcd_sdin_pz2",
"lcd_cs0_n_pn4";
nvidia,function = "spi5";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@ -240,14 +265,14 @@ lcd_sck_pz4 {
/* Apalis UART1 */
ulpi_data0 {
nvidia,pins = "ulpi_data0_po1",
"ulpi_data1_po2",
"ulpi_data2_po3",
"ulpi_data3_po4",
"ulpi_data4_po5",
"ulpi_data5_po6",
"ulpi_data6_po7",
"ulpi_data7_po0";
nvidia,pins = "ulpi_data0_po1",
"ulpi_data1_po2",
"ulpi_data2_po3",
"ulpi_data3_po4",
"ulpi_data4_po5",
"ulpi_data5_po6",
"ulpi_data6_po7",
"ulpi_data7_po0";
nvidia,function = "uarta";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@ -255,10 +280,10 @@ ulpi_data0 {
/* Apalis UART2 */
ulpi_clk_py0 {
nvidia,pins = "ulpi_clk_py0",
"ulpi_dir_py1",
"ulpi_nxt_py2",
"ulpi_stp_py3";
nvidia,pins = "ulpi_clk_py0",
"ulpi_dir_py1",
"ulpi_nxt_py2",
"ulpi_stp_py3";
nvidia,function = "uartd";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@ -266,8 +291,8 @@ ulpi_clk_py0 {
/* Apalis UART3 */
uart2_rxd_pc3 {
nvidia,pins = "uart2_rxd_pc3",
"uart2_txd_pc2";
nvidia,pins = "uart2_rxd_pc3",
"uart2_txd_pc2";
nvidia,function = "uartb";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@ -275,8 +300,8 @@ uart2_rxd_pc3 {
/* Apalis UART4 */
uart3_rxd_pw7 {
nvidia,pins = "uart3_rxd_pw7",
"uart3_txd_pw6";
nvidia,pins = "uart3_rxd_pw7",
"uart3_txd_pw6";
nvidia,function = "uartc";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@ -312,21 +337,21 @@ pv1 {
/* eMMC (On-module) */
sdmmc4_clk_pcc4 {
nvidia,pins = "sdmmc4_clk_pcc4",
"sdmmc4_rst_n_pcc3";
nvidia,pins = "sdmmc4_clk_pcc4",
"sdmmc4_rst_n_pcc3";
nvidia,function = "sdmmc4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
sdmmc4_dat0_paa0 {
nvidia,pins = "sdmmc4_dat0_paa0",
"sdmmc4_dat1_paa1",
"sdmmc4_dat2_paa2",
"sdmmc4_dat3_paa3",
"sdmmc4_dat4_paa4",
"sdmmc4_dat5_paa5",
"sdmmc4_dat6_paa6",
"sdmmc4_dat7_paa7";
nvidia,pins = "sdmmc4_dat0_paa0",
"sdmmc4_dat1_paa1",
"sdmmc4_dat2_paa2",
"sdmmc4_dat3_paa3",
"sdmmc4_dat4_paa4",
"sdmmc4_dat5_paa5",
"sdmmc4_dat6_paa6",
"sdmmc4_dat7_paa7";
nvidia,function = "sdmmc4";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@ -334,10 +359,10 @@ sdmmc4_dat0_paa0 {
/* LVDS Transceiver Configuration */
pbb0 {
nvidia,pins = "pbb0",
"pbb7",
"pcc1",
"pcc2";
nvidia,pins = "pbb0",
"pbb7",
"pcc1",
"pcc2";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@ -345,10 +370,10 @@ pbb0 {
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
pbb3 {
nvidia,pins = "pbb3",
"pbb4",
"pbb5",
"pbb6";
nvidia,pins = "pbb3",
"pbb4",
"pbb5",
"pbb6";
nvidia,function = "displayb";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@ -635,6 +660,7 @@ pmc@7000e400 {
nvidia,sys-clock-req-active-high;
};
/* eMMC */
sdhci@78000600 {
status = "okay";
bus-width = <8>;
@ -666,18 +692,40 @@ regulators {
#address-cells = <1>;
#size-cells = <0>;
sys_3v3_reg: regulator@100 {
avdd_hdmi_pll_1v8_reg: regulator@100 {
compatible = "regulator-fixed";
reg = <100>;
regulator-name = "+V1.8_AVDD_HDMI_PLL";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
enable-active-high;
gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
vin-supply = <&vio_reg>;
};
sys_3v3_reg: regulator@101 {
compatible = "regulator-fixed";
reg = <101>;
regulator-name = "3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
charge_pump_5v0_reg: regulator@101 {
avdd_hdmi_3v3_reg: regulator@102 {
compatible = "regulator-fixed";
reg = <101>;
reg = <102>;
regulator-name = "+V3.3_AVDD_HDMI";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
charge_pump_5v0_reg: regulator@103 {
compatible = "regulator-fixed";
reg = <103>;
regulator-name = "5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;

9
arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
View File

@ -55,7 +55,7 @@ i2c@7000c000 {
/* M41T0M6 real time clock on carrier board */
rtc@68 {
compatible = "stm,m41t00";
compatible = "st,m41t00";
reg = <0x68>;
};
};
@ -84,6 +84,7 @@ spidev0: spi@1 {
};
};
/* SD/MMC */
sdhci@78000200 {
status = "okay";
bus-width = <4>;
@ -136,10 +137,10 @@ clk16m: clk@1 {
gpio-keys {
compatible = "gpio-keys";
power {
label = "Power";
wakeup {
label = "SODIMM pin 45 wakeup";
gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
linux,code = <KEY_POWER>;
linux,code = <KEY_WAKEUP>;
debounce-interval = <10>;
gpio-key,wakeup;
};

196
arch/arm/boot/dts/tegra30-colibri.dtsi
View File

@ -2,8 +2,8 @@
#include "tegra30.dtsi"
/*
* Toradex Colibri T30 Device Tree
* Compatible for Revisions 1.1B/1.1C/1.1D
* Toradex Colibri T30 Module Device Tree
* Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E; IT: V1.1A
*/
/ {
model = "Toradex Colibri T30";
@ -15,8 +15,8 @@ memory {
host1x@50000000 {
hdmi@54280000 {
vdd-supply = <&sys_3v3_reg>;
pll-supply = <&vio_reg>;
vdd-supply = <&avdd_hdmi_3v3_reg>;
pll-supply = <&avdd_hdmi_pll_1v8_reg>;
nvidia,hpd-gpio =
<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
@ -39,7 +39,7 @@ pv2 {
/* Colibri Backlight PWM<A> */
sdmmc3_dat3_pb4 {
nvidia,pins = "sdmmc3_dat3_pb4";
nvidia,pins = "sdmmc3_dat3_pb4";
nvidia,function = "pwm0";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@ -66,15 +66,6 @@ lcd_m1_pw1 {
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
/* Thermal alert, need to be disabled */
lcd_dc1_pd2 {
nvidia,pins = "lcd_dc1_pd2";
nvidia,function = "rsvd3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
/* Colibri MMC */
kb_row10_ps2 {
nvidia,pins = "kb_row10_ps2";
@ -83,11 +74,11 @@ kb_row10_ps2 {
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
kb_row11_ps3 {
nvidia,pins = "kb_row11_ps3",
"kb_row12_ps4",
"kb_row13_ps5",
"kb_row14_ps6",
"kb_row15_ps7";
nvidia,pins = "kb_row11_ps3",
"kb_row12_ps4",
"kb_row13_ps5",
"kb_row14_ps6",
"kb_row15_ps7";
nvidia,function = "sdmmc2";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@ -95,17 +86,17 @@ kb_row11_ps3 {
/* Colibri SSP */
ulpi_clk_py0 {
nvidia,pins = "ulpi_clk_py0",
"ulpi_dir_py1",
"ulpi_nxt_py2",
"ulpi_stp_py3";
nvidia,pins = "ulpi_clk_py0",
"ulpi_dir_py1",
"ulpi_nxt_py2",
"ulpi_stp_py3";
nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
sdmmc3_dat6_pd3 {
nvidia,pins = "sdmmc3_dat6_pd3",
"sdmmc3_dat7_pd4";
nvidia,pins = "sdmmc3_dat6_pd3",
"sdmmc3_dat7_pd4";
nvidia,function = "spdif";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
@ -113,14 +104,14 @@ sdmmc3_dat6_pd3 {
/* Colibri UART_A */
ulpi_data0 {
nvidia,pins = "ulpi_data0_po1",
"ulpi_data1_po2",
"ulpi_data2_po3",
"ulpi_data3_po4",
"ulpi_data4_po5",
"ulpi_data5_po6",
"ulpi_data6_po7",
"ulpi_data7_po0";
nvidia,pins = "ulpi_data0_po1",
"ulpi_data1_po2",
"ulpi_data2_po3",
"ulpi_data3_po4",
"ulpi_data4_po5",
"ulpi_data5_po6",
"ulpi_data6_po7",
"ulpi_data7_po0";
nvidia,function = "uarta";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@ -128,10 +119,10 @@ ulpi_data0 {
/* Colibri UART_B */
gmi_a16_pj7 {
nvidia,pins = "gmi_a16_pj7",
"gmi_a17_pb0",
"gmi_a18_pb1",
"gmi_a19_pk7";
nvidia,pins = "gmi_a16_pj7",
"gmi_a17_pb0",
"gmi_a18_pb1",
"gmi_a19_pk7";
nvidia,function = "uartd";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@ -139,8 +130,8 @@ gmi_a16_pj7 {
/* Colibri UART_C */
uart2_rxd {
nvidia,pins = "uart2_rxd_pc3",
"uart2_txd_pc2";
nvidia,pins = "uart2_rxd_pc3",
"uart2_txd_pc2";
nvidia,function = "uartb";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@ -148,25 +139,59 @@ uart2_rxd {
/* eMMC */
sdmmc4_clk_pcc4 {
nvidia,pins = "sdmmc4_clk_pcc4",
"sdmmc4_rst_n_pcc3";
nvidia,pins = "sdmmc4_clk_pcc4",
"sdmmc4_rst_n_pcc3";
nvidia,function = "sdmmc4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
sdmmc4_dat0_paa0 {
nvidia,pins = "sdmmc4_dat0_paa0",
"sdmmc4_dat1_paa1",
"sdmmc4_dat2_paa2",
"sdmmc4_dat3_paa3",
"sdmmc4_dat4_paa4",
"sdmmc4_dat5_paa5",
"sdmmc4_dat6_paa6",
"sdmmc4_dat7_paa7";
nvidia,pins = "sdmmc4_dat0_paa0",
"sdmmc4_dat1_paa1",
"sdmmc4_dat2_paa2",
"sdmmc4_dat3_paa3",
"sdmmc4_dat4_paa4",
"sdmmc4_dat5_paa5",
"sdmmc4_dat6_paa6",
"sdmmc4_dat7_paa7";
nvidia,function = "sdmmc4";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
/* Power I2C (On-module) */
pwr_i2c_scl_pz6 {
nvidia,pins = "pwr_i2c_scl_pz6",
"pwr_i2c_sda_pz7";
nvidia,function = "i2cpwr";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
};
/*
* THERMD_ALERT#, unlatched I2C address pin of LM95245
* temperature sensor therefore requires disabling for
* now
*/
lcd_dc1_pd2 {
nvidia,pins = "lcd_dc1_pd2";
nvidia,function = "rsvd3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
/* TOUCH_PEN_INT# */
pv0 {
nvidia,pins = "pv0";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
};
};
@ -236,7 +261,7 @@ vio_reg: vio {
/*
* EN_+V3.3 switching via FET:
* +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
* see also v3_3 fixed supply
* see also 3v3 fixed supply
*/
ldo2_reg: ldo2 {
regulator-name = "en_3v3";
@ -295,6 +320,46 @@ ldo8_reg: ldo8 {
};
};
/* STMPE811 touch screen controller */
stmpe811@41 {
compatible = "st,stmpe811";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x41>;
interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio>;
interrupt-controller;
id = <0>;
blocks = <0x5>;
irq-trigger = <0x1>;
stmpe_touchscreen {
compatible = "st,stmpe-ts";
reg = <0>;
/* 3.25 MHz ADC clock speed */
st,adc-freq = <1>;
/* 8 sample average control */
st,ave-ctrl = <3>;
/* 7 length fractional part in z */
st,fraction-z = <7>;
/*
* 50 mA typical 80 mA max touchscreen drivers
* current limit value
*/
st,i-drive = <1>;
/* 12-bit ADC */
st,mod-12b = <1>;
/* internal ADC reference */
st,ref-sel = <0>;
/* ADC converstion time: 80 clocks */
st,sample-time = <4>;
/* 1 ms panel driver settling time */
st,settling = <3>;
/* 5 ms touch detect interrupt delay */
st,touch-det-delay = <5>;
};
};
/*
* LM95245 temperature sensor
* Note: OVERT_N directly connected to PMIC PWRDN
@ -331,7 +396,8 @@ pmc@7000e400 {
nvidia,sys-clock-req-active-high;
};
emmc: sdhci@78000600 {
/* eMMC */
sdhci@78000600 {
status = "okay";
bus-width = <8>;
non-removable;
@ -365,18 +431,40 @@ regulators {
#address-cells = <1>;
#size-cells = <0>;
sys_3v3_reg: regulator@100 {
avdd_hdmi_pll_1v8_reg: regulator@100 {
compatible = "regulator-fixed";
reg = <100>;
regulator-name = "+V1.8_AVDD_HDMI_PLL";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
enable-active-high;
gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
vin-supply = <&vio_reg>;
};
sys_3v3_reg: regulator@101 {
compatible = "regulator-fixed";
reg = <101>;
regulator-name = "3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
charge_pump_5v0_reg: regulator@101 {
avdd_hdmi_3v3_reg: regulator@102 {
compatible = "regulator-fixed";
reg = <101>;
reg = <102>;
regulator-name = "+V3.3_AVDD_HDMI";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
charge_pump_5v0_reg: regulator@103 {
compatible = "regulator-fixed";
reg = <103>;
regulator-name = "5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;

10
arch/arm/boot/dts/tegra30.dtsi
View File

@ -42,8 +42,8 @@ pcie-controller@00003000 {
<&tegra_car TEGRA30_CLK_CML0>;
clock-names = "pex", "afi", "pll_e", "cml";
resets = <&tegra_car 70>,
<&tegra_car 72>,
<&tegra_car 74>;
<&tegra_car 72>,
<&tegra_car 74>;
reset-names = "pex", "afi", "pcie_x";
status = "disabled";
@ -153,7 +153,7 @@ gr3d@54180000 {
&tegra_car TEGRA30_CLK_GR3D2>;
clock-names = "3d", "3d2";
resets = <&tegra_car 24>,
<&tegra_car 98>;
<&tegra_car 98>;
reset-names = "3d", "3d2";
};
@ -455,7 +455,7 @@ rtc@7000e000 {
};
i2c@7000c000 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000c000 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -660,7 +660,7 @@ hda@70030000 {
reg = <0x70030000 0x10000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_HDA>,
<&tegra_car TEGRA30_CLK_HDA2HDMI>,
<&tegra_car TEGRA30_CLK_HDA2HDMI>,
<&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
clock-names = "hda", "hda2hdmi", "hda2codec_2x";
resets = <&tegra_car 125>, /* hda */