clk: tegra: pll: Fix potential sleeping-while-atomic
Since the ->enable() callback is called with a spinlock held, we cannot call potentially blocking functions such as clk_get_rate() or clk_get_parent(), so use the unlocked versions instead. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> [rklein: Adapted from ChromeOS patch, removing pllu_enable cleanup as it isn't present upstream] Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -880,7 +880,7 @@ static int clk_plle_training(struct tegra_clk_pll *pll)
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static int clk_plle_enable(struct clk_hw *hw)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
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unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
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struct tegra_clk_pll_freq_table sel;
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u32 val;
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int err;
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@ -1378,7 +1378,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw)
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u32 val;
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int ret;
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unsigned long flags = 0;
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unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
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unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
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if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
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return -EINVAL;
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@ -2014,7 +2014,7 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw)
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u32 val;
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int ret;
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unsigned long flags = 0;
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unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
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unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
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if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
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return -EINVAL;
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