arm64: dts: add LS1046A DPAA FMan nodes
Add the DPAA 1.x FMan device tree nodes for LS1046A boards. Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -0,0 +1,48 @@
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/*
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* QorIQ FMan v3 device tree nodes for ls1046
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*
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* Copyright 2015-2016 Freescale Semiconductor Inc.
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*
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* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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*/
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&soc {
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/* include used FMan blocks */
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#include "qoriq-fman3-0.dtsi"
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#include "qoriq-fman3-0-1g-0.dtsi"
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#include "qoriq-fman3-0-1g-1.dtsi"
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#include "qoriq-fman3-0-1g-2.dtsi"
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#include "qoriq-fman3-0-1g-3.dtsi"
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#include "qoriq-fman3-0-1g-4.dtsi"
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#include "qoriq-fman3-0-1g-5.dtsi"
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#include "qoriq-fman3-0-10g-0.dtsi"
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#include "qoriq-fman3-0-10g-1.dtsi"
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};
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&fman0 {
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/* these aliases provide the FMan ports mapping */
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enet0: ethernet@e0000 {
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};
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enet1: ethernet@e2000 {
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};
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enet2: ethernet@e4000 {
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};
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enet3: ethernet@e6000 {
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};
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enet4: ethernet@e8000 {
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};
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enet5: ethernet@ea000 {
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};
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enet6: ethernet@f0000 {
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};
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enet7: ethernet@f2000 {
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};
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};
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@ -210,3 +210,5 @@ qflash0: s25fl128s@0 {
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reg = <0>;
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};
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};
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#include "fsl-ls1046-post.dtsi"
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@ -156,3 +156,63 @@ qflash1: s25fs512s@1 {
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reg = <1>;
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};
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};
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#include "fsl-ls1046-post.dtsi"
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&fman0 {
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ethernet@e4000 {
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phy-handle = <&rgmii_phy1>;
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phy-connection-type = "rgmii";
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};
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ethernet@e6000 {
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phy-handle = <&rgmii_phy2>;
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phy-connection-type = "rgmii";
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};
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ethernet@e8000 {
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phy-handle = <&sgmii_phy1>;
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phy-connection-type = "sgmii";
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};
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ethernet@ea000 {
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phy-handle = <&sgmii_phy2>;
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phy-connection-type = "sgmii";
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};
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ethernet@f0000 { /* 10GEC1 */
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phy-handle = <&aqr106_phy>;
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phy-connection-type = "xgmii";
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};
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ethernet@f2000 { /* 10GEC2 */
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fixed-link = <0 1 1000 0 0>;
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phy-connection-type = "xgmii";
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};
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mdio@fc000 {
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rgmii_phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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rgmii_phy2: ethernet-phy@2 {
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reg = <0x2>;
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};
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sgmii_phy1: ethernet-phy@3 {
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reg = <0x3>;
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};
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sgmii_phy2: ethernet-phy@4 {
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reg = <0x4>;
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};
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};
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mdio@fd000 {
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aqr106_phy: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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interrupts = <0 131 4>;
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reg = <0x0>;
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};
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};
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};
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@ -55,6 +55,15 @@ / {
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aliases {
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crypto = &crypto;
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fman0 = &fman0;
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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ethernet3 = &enet3;
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ethernet4 = &enet4;
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ethernet5 = &enet5;
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ethernet6 = &enet6;
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ethernet7 = &enet7;
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};
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cpus {
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@ -174,7 +183,7 @@ gic: interrupt-controller@1400000 {
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IRQ_TYPE_LEVEL_LOW)>;
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};
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soc {
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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