perf vendor events s390: Add JSON files for IBM zEC12 zBC12
Add CPU measurement counter facility event description files (json files) for IBM zEC12 and zBC12. Signed-off-by: Thomas Richter <tmricht@linux.vnet.ibm.com> Reviewed-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Link: http://lkml.kernel.org/r/20180326082538.2258-3-tmricht@linux.vnet.ibm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Thomas Richter
Arnaldo Carvalho de Melo
parent
0a73d21e9b
commit
3fb1a23155
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[
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{
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"EventCode": "0",
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"EventName": "CPU_CYCLES",
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"BriefDescription": "CPU Cycles",
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"PublicDescription": "Cycle Count"
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},
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{
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"EventCode": "1",
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"EventName": "INSTRUCTIONS",
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"BriefDescription": "Instructions",
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"PublicDescription": "Instruction Count"
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},
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{
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"EventCode": "2",
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"EventName": "L1I_DIR_WRITES",
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"BriefDescription": "L1I Directory Writes",
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"PublicDescription": "Level-1 I-Cache Directory Write Count"
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},
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{
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"EventCode": "3",
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"EventName": "L1I_PENALTY_CYCLES",
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"BriefDescription": "L1I Penalty Cycles",
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"PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
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},
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{
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"EventCode": "4",
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"EventName": "L1D_DIR_WRITES",
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"BriefDescription": "L1D Directory Writes",
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"PublicDescription": "Level-1 D-Cache Directory Write Count"
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},
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{
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"EventCode": "5",
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"EventName": "L1D_PENALTY_CYCLES",
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"BriefDescription": "L1D Penalty Cycles",
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"PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
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},
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{
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"EventCode": "32",
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"EventName": "PROBLEM_STATE_CPU_CYCLES",
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"BriefDescription": "Problem-State CPU Cycles",
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"PublicDescription": "Problem-State Cycle Count"
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},
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{
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"EventCode": "33",
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"EventName": "PROBLEM_STATE_INSTRUCTIONS",
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"BriefDescription": "Problem-State Instructions",
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"PublicDescription": "Problem-State Instruction Count"
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},
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{
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"EventCode": "34",
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"EventName": "PROBLEM_STATE_L1I_DIR_WRITES",
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"BriefDescription": "Problem-State L1I Directory Writes",
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"PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count"
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},
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{
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"EventCode": "35",
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"EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES",
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"BriefDescription": "Problem-State L1I Penalty Cycles",
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"PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count"
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},
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{
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"EventCode": "36",
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"EventName": "PROBLEM_STATE_L1D_DIR_WRITES",
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"BriefDescription": "Problem-State L1D Directory Writes",
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"PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count"
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},
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{
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"EventCode": "37",
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"EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES",
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"BriefDescription": "Problem-State L1D Penalty Cycles",
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"PublicDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count"
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},
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]
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[
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{
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"EventCode": "64",
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"EventName": "PRNG_FUNCTIONS",
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"BriefDescription": "PRNG Functions",
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"PublicDescription": "Total number of the PRNG functions issued by the CPU"
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},
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{
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"EventCode": "65",
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"EventName": "PRNG_CYCLES",
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"BriefDescription": "PRNG Cycles",
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"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU"
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},
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{
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"EventCode": "66",
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"EventName": "PRNG_BLOCKED_FUNCTIONS",
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"BriefDescription": "PRNG Blocked Functions",
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"PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
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},
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{
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"EventCode": "67",
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"EventName": "PRNG_BLOCKED_CYCLES",
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"BriefDescription": "PRNG Blocked Cycles",
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"PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
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},
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{
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"EventCode": "68",
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"EventName": "SHA_FUNCTIONS",
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"BriefDescription": "SHA Functions",
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"PublicDescription": "Total number of SHA functions issued by the CPU"
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},
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{
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"EventCode": "69",
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"EventName": "SHA_CYCLES",
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"BriefDescription": "SHA Cycles",
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"PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU"
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},
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{
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"EventCode": "70",
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"EventName": "SHA_BLOCKED_FUNCTIONS",
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"BriefDescription": "SHA Blocked Functions",
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"PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU"
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},
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{
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"EventCode": "71",
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"EventName": "SHA_BLOCKED_CYCLES",
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"BriefDescription": "SHA Bloced Cycles",
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"PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU"
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},
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{
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"EventCode": "72",
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"EventName": "DEA_FUNCTIONS",
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"BriefDescription": "DEA Functions",
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"PublicDescription": "Total number of the DEA functions issued by the CPU"
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},
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{
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"EventCode": "73",
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"EventName": "DEA_CYCLES",
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"BriefDescription": "DEA Cycles",
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"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU"
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},
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{
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"EventCode": "74",
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"EventName": "DEA_BLOCKED_FUNCTIONS",
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"BriefDescription": "DEA Blocked Functions",
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"PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
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},
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{
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"EventCode": "75",
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"EventName": "DEA_BLOCKED_CYCLES",
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"BriefDescription": "DEA Blocked Cycles",
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"PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
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},
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{
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"EventCode": "76",
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"EventName": "AES_FUNCTIONS",
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"BriefDescription": "AES Functions",
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"PublicDescription": "Total number of AES functions issued by the CPU"
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},
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{
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"EventCode": "77",
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"EventName": "AES_CYCLES",
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"BriefDescription": "AES Cycles",
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"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU"
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},
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{
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"EventCode": "78",
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"EventName": "AES_BLOCKED_FUNCTIONS",
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"BriefDescription": "AES Blocked Functions",
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"PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
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},
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{
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"EventCode": "79",
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"EventName": "AES_BLOCKED_CYCLES",
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"BriefDescription": "AES Blocked Cycles",
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"PublicDescription": "Total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
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},
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]
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[
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{
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"EventCode": "128",
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"EventName": "DTLB1_MISSES",
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"BriefDescription": "DTLB1 Misses",
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"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB1 miss is in progress."
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},
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{
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"EventCode": "129",
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"EventName": "ITLB1_MISSES",
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"BriefDescription": "ITLB1 Misses",
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"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle a ITLB1 miss is in progress."
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},
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{
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"EventCode": "130",
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"EventName": "L1D_L2I_SOURCED_WRITES",
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"BriefDescription": "L1D L2I Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
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},
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{
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"EventCode": "131",
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"EventName": "L1I_L2I_SOURCED_WRITES",
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"BriefDescription": "L1I L2I Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
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},
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{
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"EventCode": "132",
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"EventName": "L1D_L2D_SOURCED_WRITES",
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"BriefDescription": "L1D L2D Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache"
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},
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{
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"EventCode": "133",
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"EventName": "DTLB1_WRITES",
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"BriefDescription": "DTLB1 Writes",
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"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer"
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},
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{
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"EventCode": "135",
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"EventName": "L1D_LMEM_SOURCED_WRITES",
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"BriefDescription": "L1D Local Memory Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)"
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},
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{
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"EventCode": "137",
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"EventName": "L1I_LMEM_SOURCED_WRITES",
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"BriefDescription": "L1I Local Memory Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)"
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},
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{
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"EventCode": "138",
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"EventName": "L1D_RO_EXCL_WRITES",
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"BriefDescription": "L1D Read-only Exclusive Writes",
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"PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line"
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},
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{
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"EventCode": "139",
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"EventName": "DTLB1_HPAGE_WRITES",
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"BriefDescription": "DTLB1 One-Megabyte Page Writes",
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"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page"
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},
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{
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"EventCode": "140",
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"EventName": "ITLB1_WRITES",
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"BriefDescription": "ITLB1 Writes",
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"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer"
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},
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{
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"EventCode": "141",
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"EventName": "TLB2_PTE_WRITES",
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"BriefDescription": "TLB2 PTE Writes",
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"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays"
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},
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{
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"EventCode": "142",
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"EventName": "TLB2_CRSTE_HPAGE_WRITES",
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"BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
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"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation"
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},
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{
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"EventCode": "143",
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"EventName": "TLB2_CRSTE_WRITES",
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"BriefDescription": "TLB2 CRSTE Writes",
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"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays"
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},
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{
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"EventCode": "144",
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"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
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"BriefDescription": "L1D On-Chip L3 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention"
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},
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{
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"EventCode": "145",
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"EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES",
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"BriefDescription": "L1D Off-Chip L3 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention"
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},
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{
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"EventCode": "146",
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"EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES",
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"BriefDescription": "L1D Off-Book L3 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention"
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},
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{
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"EventCode": "147",
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"EventName": "L1D_ONBOOK_L4_SOURCED_WRITES",
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"BriefDescription": "L1D On-Book L4 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Book Level-4 cache"
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},
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{
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"EventCode": "148",
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"EventName": "L1D_OFFBOOK_L4_SOURCED_WRITES",
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"BriefDescription": "L1D Off-Book L4 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-4 cache"
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},
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{
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"EventCode": "149",
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"EventName": "TX_NC_TEND",
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"BriefDescription": "Completed TEND instructions in non-constrained TX mode",
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"PublicDescription": "A TEND instruction has completed in a nonconstrained transactional-execution mode"
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},
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{
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"EventCode": "150",
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"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV",
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"BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from a On Chip Level-3 cache with intervention"
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},
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{
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"EventCode": "151",
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"EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES_IV",
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"BriefDescription": "L1D Off-Chip L3 Sourced Writes with Intervention",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention"
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},
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{
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"EventCode": "152",
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"EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES_IV",
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"BriefDescription": "L1D Off-Book L3 Sourced Writes with Intervention",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention"
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},
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{
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"EventCode": "153",
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"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
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"BriefDescription": "L1I On-Chip L3 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention"
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},
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{
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"EventCode": "154",
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"EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES",
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"BriefDescription": "L1I Off-Chip L3 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention"
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},
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{
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"EventCode": "155",
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"EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES",
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"BriefDescription": "L1I Off-Book L3 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention"
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},
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{
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"EventCode": "156",
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"EventName": "L1I_ONBOOK_L4_SOURCED_WRITES",
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"BriefDescription": "L1I On-Book L4 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Book Level-4 cache"
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},
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{
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"EventCode": "157",
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"EventName": "L1I_OFFBOOK_L4_SOURCED_WRITES",
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"BriefDescription": "L1I Off-Book L4 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-4 cache"
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},
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{
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"EventCode": "158",
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"EventName": "TX_C_TEND",
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"BriefDescription": "Completed TEND instructions in constrained TX mode",
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"PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode"
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},
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{
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"EventCode": "159",
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"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV",
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"BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention"
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},
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{
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"EventCode": "160",
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"EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES_IV",
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"BriefDescription": "L1I Off-Chip L3 Sourced Writes with Intervention",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention"
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},
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{
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"EventCode": "161",
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"EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES_IV",
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"BriefDescription": "L1I Off-Book L3 Sourced Writes with Intervention",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention"
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},
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{
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"EventCode": "177",
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"EventName": "TX_NC_TABORT",
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"BriefDescription": "Aborted transactions in non-constrained TX mode",
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"PublicDescription": "A transaction abort has occurred in a nonconstrained transactional-execution mode"
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},
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{
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"EventCode": "178",
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"EventName": "TX_C_TABORT_NO_SPECIAL",
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"BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic",
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"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete"
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},
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{
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"EventCode": "179",
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"EventName": "TX_C_TABORT_SPECIAL",
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"BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
|
||||
"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete"
|
||||
},
|
||||
]
|
||||
|
|
@ -1,3 +1,4 @@
|
|||
Family-model,Version,Filename,EventType
|
||||
209[78],1,cf_z10,core
|
||||
281[78],1,cf_z196,core
|
||||
282[78],1,cf_zec12,core
|
||||
|
|
|
|||
|
Loading…
Reference in New Issue