net: smmac: allow configuring lower pbl values
The driver currently always sets the PBLx8/PBLx4 bit, which means that the pbl values configured via the pbl/txpbl/rxpbl DT properties are always multiplied by 8/4 in the hardware. In order to allow the DT to configure lower pbl values, while at the same time not changing behavior of any existing device trees using the pbl/txpbl/rxpbl settings, add a property to disable the multiplication of the pbl by 8/4 in the hardware. Suggested-by: Rabin Vincent <rabinv@axis.com> Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Acked-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -39,6 +39,8 @@ Optional properties:
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If set, DMA tx will use this value rather than snps,pbl.
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- snps,rxpbl Rx Programmable Burst Length. Only for GMAC and newer.
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If set, DMA rx will use this value rather than snps,pbl.
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- snps,no-pbl-x8 Don't multiply the pbl/txpbl/rxpbl values by 8.
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For core rev < 3.50, don't multiply the values by 4.
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- snps,aal Address-Aligned Beats
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- snps,fixed-burst Program the DMA to use the fixed burst mode
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- snps,mixed-burst Program the DMA to use the mixed burst mode
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@ -152,8 +152,9 @@ Where:
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o dma_cfg: internal DMA parameters
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o pbl: the Programmable Burst Length is maximum number of beats to
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be transferred in one DMA transaction.
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GMAC also enables the 4xPBL by default.
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GMAC also enables the 4xPBL by default. (8xPBL for GMAC 3.50 and newer)
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o txpbl/rxpbl: GMAC and newer supports independent DMA pbl for tx/rx.
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o pblx8: Enable 8xPBL (4xPBL for core rev < 3.50). Enabled by default.
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o fixed_burst/mixed_burst/aal
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o clk_csr: fixed CSR Clock range selection.
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o has_gmac: uses the GMAC core.
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@ -208,6 +209,7 @@ struct stmmac_dma_cfg {
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int pbl;
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int txpbl;
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int rxpbl;
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bool pblx8;
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int fixed_burst;
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int mixed_burst;
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bool aal;
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@ -219,6 +221,7 @@ Where:
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If set, DMA tx will use this value rather than pbl.
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o rxpbl: Receive Programmable Burst Length. Only for GMAC and newer.
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If set, DMA rx will use this value rather than pbl.
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o pblx8: Enable 8xPBL (4xPBL for core rev < 3.50). Enabled by default.
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o fixed_burst: program the DMA to use the fixed burst mode
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o mixed_burst: program the DMA to use the mixed burst mode
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o aal: Address-Aligned Beats
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@ -98,7 +98,8 @@ static void dwmac1000_dma_init(void __iomem *ioaddr,
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* Note: before stmmac core 3.50 this mode bit was 4xPBL, and
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* post 3.5 mode bit acts as 8*PBL.
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*/
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value |= DMA_BUS_MODE_MAXPBL;
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if (dma_cfg->pblx8)
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value |= DMA_BUS_MODE_MAXPBL;
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value |= DMA_BUS_MODE_USP;
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value &= ~(DMA_BUS_MODE_PBL_MASK | DMA_BUS_MODE_RPBL_MASK);
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value |= (txpbl << DMA_BUS_MODE_PBL_SHIFT);
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@ -84,7 +84,8 @@ static void dwmac4_dma_init_channel(void __iomem *ioaddr,
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* on each channel
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*/
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value = readl(ioaddr + DMA_CHAN_CONTROL(channel));
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value = value | DMA_BUS_MODE_PBL;
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if (dma_cfg->pblx8)
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value = value | DMA_BUS_MODE_PBL;
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writel(value, ioaddr + DMA_CHAN_CONTROL(channel));
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value = readl(ioaddr + DMA_CHAN_TX_CONTROL(channel));
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@ -81,6 +81,7 @@ static void stmmac_default_data(struct plat_stmmacenet_data *plat)
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plat->mdio_bus_data->phy_mask = 0;
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plat->dma_cfg->pbl = 32;
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plat->dma_cfg->pblx8 = true;
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/* TODO: AXI */
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/* Set default value for multicast hash bins */
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@ -115,6 +116,7 @@ static int quark_default_data(struct plat_stmmacenet_data *plat,
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plat->mdio_bus_data->phy_mask = 0;
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plat->dma_cfg->pbl = 16;
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plat->dma_cfg->pblx8 = true;
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plat->dma_cfg->fixed_burst = 1;
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/* AXI (TODO) */
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@ -317,6 +317,7 @@ stmmac_probe_config_dt(struct platform_device *pdev, const char **mac)
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dma_cfg->pbl = DEFAULT_DMA_PBL;
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of_property_read_u32(np, "snps,txpbl", &dma_cfg->txpbl);
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of_property_read_u32(np, "snps,rxpbl", &dma_cfg->rxpbl);
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dma_cfg->pblx8 = !of_property_read_bool(np, "snps,no-pbl-x8");
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dma_cfg->aal = of_property_read_bool(np, "snps,aal");
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dma_cfg->fixed_burst = of_property_read_bool(np, "snps,fixed-burst");
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@ -90,6 +90,7 @@ struct stmmac_dma_cfg {
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int pbl;
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int txpbl;
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int rxpbl;
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bool pblx8;
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int fixed_burst;
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int mixed_burst;
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bool aal;
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