spi: Fixes for v5.19
A bunch of driver specific fixes, plus a fix for spi-mem's status polling for devices that use GPIO chip selects and a DT bindings examples fix that helps with the validation work. -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEreZoqmdXGLWf4p/qJNaLcl1Uh9AFAmK160MACgkQJNaLcl1U h9D9pQf+PDg9PFz++i9SVBvRGJn6YNXpgUXSPlN39KvSUgf4esc9oKJ53NVwA3g5 BdaTAhZIP6ZdvfBfy1J1NggwVA/1T8yvQZ4hafqJaAyqydO4OvtF0lN9xe++Y0e6 VVYZ1Y63F21hstxVjBwrdsUoNb/pBr2ltz02W6DkrLsa7LtWESSzblVJ0lvDP2lU 61ycBHgM6kyxVpgJCWB63VnK1RyLFTVBo9DZM0W4RuRQ3NYEfg5mfDy5xhGlIodV k0gIZ6UlxuumEuiuGgeoW2sy4zWfsnEQvyk7KUiknYur25sZTfPImznCr8MC53j3 gGeKaY3vuHnRSfPsOoQfc7pWnjmjQQ== =m1g1 -----END PGP SIGNATURE----- Merge tag 'spi-fix-v5.19-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fixes from Mark Brown: "A bunch of driver specific fixes, plus a fix for spi-mem's status polling for devices that use GPIO chip selects and a DT bindings examples fix that helps with the validation work" * tag 'spi-fix-v5.19-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: rockchip: Unmask IRQ at the final to avoid preemption spi: dt-bindings: Fix unevaluatedProperties warnings in examples spi: spi-mem: Fix spi_mem_poll_status() spi: cadence: Detect transmit FIFO depth spi: spi-cadence: Fix SPI CS gets toggling sporadically
This commit is contained in:
Linus Torvalds
commit
4039974f3b
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@ -47,6 +47,5 @@ examples:
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clocks = <&clkcfg CLK_SPI0>;
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interrupt-parent = <&plic>;
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interrupts = <54>;
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spi-max-frequency = <25000000>;
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};
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...
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@ -110,7 +110,6 @@ examples:
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pinctrl-names = "default";
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pinctrl-0 = <&qup_spi1_default>;
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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@ -69,6 +69,7 @@
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#define CDNS_SPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */
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#define CDNS_SPI_SS_SHIFT 10 /* Slave Select field shift in CR */
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#define CDNS_SPI_SS0 0x1 /* Slave Select zero */
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#define CDNS_SPI_NOSS 0x3C /* No Slave select */
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/*
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* SPI Interrupt Registers bit Masks
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@ -92,9 +93,6 @@
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#define CDNS_SPI_ER_ENABLE 0x00000001 /* SPI Enable Bit Mask */
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#define CDNS_SPI_ER_DISABLE 0x0 /* SPI Disable Bit Mask */
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/* SPI FIFO depth in bytes */
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#define CDNS_SPI_FIFO_DEPTH 128
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/* Default number of chip select lines */
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#define CDNS_SPI_DEFAULT_NUM_CS 4
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@ -110,6 +108,7 @@
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* @rx_bytes: Number of bytes requested
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* @dev_busy: Device busy flag
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* @is_decoded_cs: Flag for decoder property set or not
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* @tx_fifo_depth: Depth of the TX FIFO
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*/
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struct cdns_spi {
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void __iomem *regs;
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@ -123,6 +122,7 @@ struct cdns_spi {
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int rx_bytes;
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u8 dev_busy;
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u32 is_decoded_cs;
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unsigned int tx_fifo_depth;
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};
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/* Macros for the SPI controller read/write */
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@ -304,7 +304,7 @@ static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi)
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{
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unsigned long trans_cnt = 0;
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while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) &&
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while ((trans_cnt < xspi->tx_fifo_depth) &&
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(xspi->tx_bytes > 0)) {
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/* When xspi in busy condition, bytes may send failed,
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@ -450,19 +450,42 @@ static int cdns_prepare_transfer_hardware(struct spi_master *master)
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* @master: Pointer to the spi_master structure which provides
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* information about the controller.
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*
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* This function disables the SPI master controller.
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* This function disables the SPI master controller when no slave selected.
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*
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* Return: 0 always
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*/
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static int cdns_unprepare_transfer_hardware(struct spi_master *master)
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{
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struct cdns_spi *xspi = spi_master_get_devdata(master);
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u32 ctrl_reg;
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cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
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/* Disable the SPI if slave is deselected */
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ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
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ctrl_reg = (ctrl_reg & CDNS_SPI_CR_SSCTRL) >> CDNS_SPI_SS_SHIFT;
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if (ctrl_reg == CDNS_SPI_NOSS)
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cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
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return 0;
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}
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/**
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* cdns_spi_detect_fifo_depth - Detect the FIFO depth of the hardware
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* @xspi: Pointer to the cdns_spi structure
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*
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* The depth of the TX FIFO is a synthesis configuration parameter of the SPI
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* IP. The FIFO threshold register is sized so that its maximum value can be the
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* FIFO size - 1. This is used to detect the size of the FIFO.
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*/
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static void cdns_spi_detect_fifo_depth(struct cdns_spi *xspi)
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{
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/* The MSBs will get truncated giving us the size of the FIFO */
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cdns_spi_write(xspi, CDNS_SPI_THLD, 0xffff);
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xspi->tx_fifo_depth = cdns_spi_read(xspi, CDNS_SPI_THLD) + 1;
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/* Reset to default */
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cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
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}
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/**
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* cdns_spi_probe - Probe method for the SPI driver
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* @pdev: Pointer to the platform_device structure
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@ -535,6 +558,8 @@ static int cdns_spi_probe(struct platform_device *pdev)
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if (ret < 0)
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xspi->is_decoded_cs = 0;
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cdns_spi_detect_fifo_depth(xspi);
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/* SPI controller initializations */
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cdns_spi_init_hw(xspi);
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@ -808,7 +808,7 @@ int spi_mem_poll_status(struct spi_mem *mem,
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op->data.dir != SPI_MEM_DATA_IN)
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return -EINVAL;
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if (ctlr->mem_ops && ctlr->mem_ops->poll_status) {
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if (ctlr->mem_ops && ctlr->mem_ops->poll_status && !mem->spi->cs_gpiod) {
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ret = spi_mem_access_start(mem);
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if (ret)
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return ret;
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@ -381,15 +381,18 @@ static int rockchip_spi_prepare_irq(struct rockchip_spi *rs,
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rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
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rs->rx_left = xfer->len / rs->n_bytes;
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if (rs->cs_inactive)
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writel_relaxed(INT_RF_FULL | INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
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else
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writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR);
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writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
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spi_enable_chip(rs, true);
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if (rs->tx_left)
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rockchip_spi_pio_writer(rs);
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if (rs->cs_inactive)
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writel_relaxed(INT_RF_FULL | INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
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else
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writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR);
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/* 1 means the transfer is in progress */
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return 1;
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}
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