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drm/nvc0/fifo: sched intr 

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2014-02-22 01:18:46 +10:00
parent d439a5acbc
commit 4047653925
1 changed files with 22 additions and 2 deletions
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24
drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
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@ -371,6 +371,27 @@ nvc0_fifo_swmthd(struct nvc0_fifo_priv *priv, u32 chid, u32 mthd, u32 data)
return ret; return ret;
} }
static const struct nouveau_enum
nvc0_fifo_sched_reason[] = {
{ 0x0a, "CTXSW_TIMEOUT" },
{}
};
static void
nvc0_fifo_intr_sched(struct nvc0_fifo_priv *priv)
{
u32 intr = nv_rd32(priv, 0x00254c);
u32 code = intr & 0x000000ff;
const struct nouveau_enum *en;
char enunk[6] = "";
en = nouveau_enum_find(nvc0_fifo_sched_reason, code);
if (!en)
snprintf(enunk, sizeof(enunk), "UNK%02x", code);
nv_error(priv, "SCHED_ERROR [ %s ]\n", en ? en->name : enunk);
}
static const struct nouveau_enum static const struct nouveau_enum
nvc0_fifo_fault_engine[] = { nvc0_fifo_fault_engine[] = {
{ 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR }, { 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR },
@ -603,8 +624,7 @@ nvc0_fifo_intr(struct nouveau_subdev *subdev)
} }
if (stat & 0x00000100) { if (stat & 0x00000100) {
u32 intr = nv_rd32(priv, 0x00254c); nvc0_fifo_intr_sched(priv);
nv_warn(priv, "INTR 0x00000100: 0x%08x\n", intr);
nv_wr32(priv, 0x002100, 0x00000100); nv_wr32(priv, 0x002100, 0x00000100);
stat &= ~0x00000100; stat &= ~0x00000100;
} }