iio: adxl372: New driver for Analog Devices ADXL372 Accelerometer
This patch adds basic support for Analog Devices ADXL372 SPI-Bus Three-Axis Digital Accelerometer. The device is probed and configured the with some initial default values. With this basic driver, it is possible to read raw acceleration data. Datasheet: http://www.analog.com/media/en/technical-documentation/data-sheets/ADXL372.pdf Signed-off-by: Stefan Popa <stefan.popa@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Stefan Popa
Jonathan Cameron
parent
4d0434f129
commit
4097da40f9
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@ -543,6 +543,12 @@ W: http://ez.analog.com/community/linux-device-drivers
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S: Supported
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F: drivers/input/misc/adxl34x.c
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ADXL372 THREE-AXIS DIGITAL ACCELEROMETER DRIVER
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M: Stefan Popa <stefan.popa@analog.com>
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W: http://ez.analog.com/community/linux-device-drivers
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S: Supported
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F: drivers/iio/accel/adxl372.c
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AF9013 MEDIA DRIVER
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M: Antti Palosaari <crope@iki.fi>
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L: linux-media@vger.kernel.org
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@ -60,6 +60,17 @@ config ADXL345_SPI
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will be called adxl345_spi and you will also get adxl345_core
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for the core module.
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config ADXL372
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tristate "Analog Devices ADXL372 3-Axis Accelerometer Driver"
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depends on SPI
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select IIO_BUFFER
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select IIO_TRIGGERED_BUFFER
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help
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Say yes here to add support for the Analog Devices ADXL372 triaxial
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acceleration sensor.
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To compile this driver as a module, choose M here: the
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module will be called adxl372.
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config BMA180
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tristate "Bosch BMA180/BMA250 3-Axis Accelerometer Driver"
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depends on I2C
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@ -9,6 +9,7 @@ obj-$(CONFIG_ADIS16209) += adis16209.o
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obj-$(CONFIG_ADXL345) += adxl345_core.o
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obj-$(CONFIG_ADXL345_I2C) += adxl345_i2c.o
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obj-$(CONFIG_ADXL345_SPI) += adxl345_spi.o
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obj-$(CONFIG_ADXL372) += adxl372.o
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obj-$(CONFIG_BMA180) += bma180.o
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obj-$(CONFIG_BMA220) += bma220_spi.o
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obj-$(CONFIG_BMC150_ACCEL) += bmc150-accel-core.o
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@ -0,0 +1,525 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* ADXL372 3-Axis Digital Accelerometer SPI driver
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*
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* Copyright 2018 Analog Devices Inc.
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*/
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#include <linux/bitops.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include <linux/spi/spi.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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/* ADXL372 registers definition */
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#define ADXL372_DEVID 0x00
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#define ADXL372_DEVID_MST 0x01
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#define ADXL372_PARTID 0x02
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#define ADXL372_REVID 0x03
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#define ADXL372_STATUS_1 0x04
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#define ADXL372_STATUS_2 0x05
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#define ADXL372_FIFO_ENTRIES_2 0x06
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#define ADXL372_FIFO_ENTRIES_1 0x07
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#define ADXL372_X_DATA_H 0x08
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#define ADXL372_X_DATA_L 0x09
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#define ADXL372_Y_DATA_H 0x0A
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#define ADXL372_Y_DATA_L 0x0B
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#define ADXL372_Z_DATA_H 0x0C
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#define ADXL372_Z_DATA_L 0x0D
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#define ADXL372_X_MAXPEAK_H 0x15
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#define ADXL372_X_MAXPEAK_L 0x16
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#define ADXL372_Y_MAXPEAK_H 0x17
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#define ADXL372_Y_MAXPEAK_L 0x18
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#define ADXL372_Z_MAXPEAK_H 0x19
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#define ADXL372_Z_MAXPEAK_L 0x1A
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#define ADXL372_OFFSET_X 0x20
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#define ADXL372_OFFSET_Y 0x21
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#define ADXL372_OFFSET_Z 0x22
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#define ADXL372_X_THRESH_ACT_H 0x23
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#define ADXL372_X_THRESH_ACT_L 0x24
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#define ADXL372_Y_THRESH_ACT_H 0x25
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#define ADXL372_Y_THRESH_ACT_L 0x26
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#define ADXL372_Z_THRESH_ACT_H 0x27
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#define ADXL372_Z_THRESH_ACT_L 0x28
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#define ADXL372_TIME_ACT 0x29
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#define ADXL372_X_THRESH_INACT_H 0x2A
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#define ADXL372_X_THRESH_INACT_L 0x2B
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#define ADXL372_Y_THRESH_INACT_H 0x2C
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#define ADXL372_Y_THRESH_INACT_L 0x2D
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#define ADXL372_Z_THRESH_INACT_H 0x2E
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#define ADXL372_Z_THRESH_INACT_L 0x2F
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#define ADXL372_TIME_INACT_H 0x30
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#define ADXL372_TIME_INACT_L 0x31
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#define ADXL372_X_THRESH_ACT2_H 0x32
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#define ADXL372_X_THRESH_ACT2_L 0x33
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#define ADXL372_Y_THRESH_ACT2_H 0x34
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#define ADXL372_Y_THRESH_ACT2_L 0x35
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#define ADXL372_Z_THRESH_ACT2_H 0x36
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#define ADXL372_Z_THRESH_ACT2_L 0x37
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#define ADXL372_HPF 0x38
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#define ADXL372_FIFO_SAMPLES 0x39
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#define ADXL372_FIFO_CTL 0x3A
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#define ADXL372_INT1_MAP 0x3B
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#define ADXL372_INT2_MAP 0x3C
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#define ADXL372_TIMING 0x3D
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#define ADXL372_MEASURE 0x3E
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#define ADXL372_POWER_CTL 0x3F
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#define ADXL372_SELF_TEST 0x40
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#define ADXL372_RESET 0x41
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#define ADXL372_FIFO_DATA 0x42
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#define ADXL372_DEVID_VAL 0xAD
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#define ADXL372_PARTID_VAL 0xFA
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#define ADXL372_RESET_CODE 0x52
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/* ADXL372_POWER_CTL */
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#define ADXL372_POWER_CTL_MODE_MSK GENMASK_ULL(1, 0)
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#define ADXL372_POWER_CTL_MODE(x) (((x) & 0x3) << 0)
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/* ADXL372_MEASURE */
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#define ADXL372_MEASURE_LINKLOOP_MSK GENMASK_ULL(5, 4)
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#define ADXL372_MEASURE_LINKLOOP_MODE(x) (((x) & 0x3) << 4)
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#define ADXL372_MEASURE_BANDWIDTH_MSK GENMASK_ULL(2, 0)
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#define ADXL372_MEASURE_BANDWIDTH_MODE(x) (((x) & 0x7) << 0)
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/* ADXL372_TIMING */
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#define ADXL372_TIMING_ODR_MSK GENMASK_ULL(7, 5)
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#define ADXL372_TIMING_ODR_MODE(x) (((x) & 0x7) << 5)
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/* ADXL372_FIFO_CTL */
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#define ADXL372_FIFO_CTL_FORMAT_MSK GENMASK(5, 3)
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#define ADXL372_FIFO_CTL_FORMAT_MODE(x) (((x) & 0x7) << 3)
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#define ADXL372_FIFO_CTL_MODE_MSK GENMASK(2, 1)
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#define ADXL372_FIFO_CTL_MODE_MODE(x) (((x) & 0x3) << 1)
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#define ADXL372_FIFO_CTL_SAMPLES_MSK BIT(1)
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#define ADXL372_FIFO_CTL_SAMPLES_MODE(x) (((x) > 0xFF) ? 1 : 0)
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/* ADXL372_STATUS_1 */
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#define ADXL372_STATUS_1_DATA_RDY(x) (((x) >> 0) & 0x1)
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#define ADXL372_STATUS_1_FIFO_RDY(x) (((x) >> 1) & 0x1)
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#define ADXL372_STATUS_1_FIFO_FULL(x) (((x) >> 2) & 0x1)
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#define ADXL372_STATUS_1_FIFO_OVR(x) (((x) >> 3) & 0x1)
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#define ADXL372_STATUS_1_USR_NVM_BUSY(x) (((x) >> 5) & 0x1)
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#define ADXL372_STATUS_1_AWAKE(x) (((x) >> 6) & 0x1)
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#define ADXL372_STATUS_1_ERR_USR_REGS(x) (((x) >> 7) & 0x1)
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/* ADXL372_INT1_MAP */
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#define ADXL372_INT1_MAP_DATA_RDY_MSK BIT(0)
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#define ADXL372_INT1_MAP_DATA_RDY_MODE(x) (((x) & 0x1) << 0)
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#define ADXL372_INT1_MAP_FIFO_RDY_MSK BIT(1)
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#define ADXL372_INT1_MAP_FIFO_RDY_MODE(x) (((x) & 0x1) << 1)
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#define ADXL372_INT1_MAP_FIFO_FULL_MSK BIT(2)
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#define ADXL372_INT1_MAP_FIFO_FULL_MODE(x) (((x) & 0x1) << 2)
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#define ADXL372_INT1_MAP_FIFO_OVR_MSK BIT(3)
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#define ADXL372_INT1_MAP_FIFO_OVR_MODE(x) (((x) & 0x1) << 3)
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#define ADXL372_INT1_MAP_INACT_MSK BIT(4)
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#define ADXL372_INT1_MAP_INACT_MODE(x) (((x) & 0x1) << 4)
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#define ADXL372_INT1_MAP_ACT_MSK BIT(5)
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#define ADXL372_INT1_MAP_ACT_MODE(x) (((x) & 0x1) << 5)
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#define ADXL372_INT1_MAP_AWAKE_MSK BIT(6)
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#define ADXL372_INT1_MAP_AWAKE_MODE(x) (((x) & 0x1) << 6)
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#define ADXL372_INT1_MAP_LOW_MSK BIT(7)
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#define ADXL372_INT1_MAP_LOW_MODE(x) (((x) & 0x1) << 7)
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/*
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* At +/- 200g with 12-bit resolution, scale is computed as:
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* (200 + 200) * 9.81 / (2^12 - 1) = 0.958241
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*/
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#define ADXL372_USCALE 958241
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enum adxl372_op_mode {
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ADXL372_STANDBY,
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ADXL372_WAKE_UP,
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ADXL372_INSTANT_ON,
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ADXL372_FULL_BW_MEASUREMENT,
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};
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enum adxl372_act_proc_mode {
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ADXL372_DEFAULT,
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ADXL372_LINKED,
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ADXL372_LOOPED,
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};
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enum adxl372_th_activity {
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ADXL372_ACTIVITY,
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ADXL372_ACTIVITY2,
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ADXL372_INACTIVITY,
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};
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enum adxl372_odr {
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ADXL372_ODR_400HZ,
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ADXL372_ODR_800HZ,
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ADXL372_ODR_1600HZ,
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ADXL372_ODR_3200HZ,
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ADXL372_ODR_6400HZ,
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};
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enum adxl372_bandwidth {
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ADXL372_BW_200HZ,
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ADXL372_BW_400HZ,
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ADXL372_BW_800HZ,
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ADXL372_BW_1600HZ,
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ADXL372_BW_3200HZ,
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};
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static const unsigned int adxl372_th_reg_high_addr[3] = {
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[ADXL372_ACTIVITY] = ADXL372_X_THRESH_ACT_H,
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[ADXL372_ACTIVITY2] = ADXL372_X_THRESH_ACT2_H,
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[ADXL372_INACTIVITY] = ADXL372_X_THRESH_INACT_H,
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};
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#define ADXL372_ACCEL_CHANNEL(index, reg, axis) { \
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.type = IIO_ACCEL, \
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.address = reg, \
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.modified = 1, \
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.channel2 = IIO_MOD_##axis, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
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}
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static const struct iio_chan_spec adxl372_channels[] = {
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ADXL372_ACCEL_CHANNEL(0, ADXL372_X_DATA_H, X),
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ADXL372_ACCEL_CHANNEL(1, ADXL372_Y_DATA_H, Y),
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ADXL372_ACCEL_CHANNEL(2, ADXL372_Z_DATA_H, Z),
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};
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struct adxl372_state {
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struct spi_device *spi;
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struct regmap *regmap;
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enum adxl372_op_mode op_mode;
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enum adxl372_act_proc_mode act_proc_mode;
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enum adxl372_odr odr;
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enum adxl372_bandwidth bw;
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u32 act_time_ms;
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u32 inact_time_ms;
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};
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static int adxl372_read_axis(struct adxl372_state *st, u8 addr)
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{
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__be16 regval;
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int ret;
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ret = regmap_bulk_read(st->regmap, addr, ®val, sizeof(regval));
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if (ret < 0)
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return ret;
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return be16_to_cpu(regval);
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}
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static int adxl372_set_op_mode(struct adxl372_state *st,
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enum adxl372_op_mode op_mode)
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{
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int ret;
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ret = regmap_update_bits(st->regmap, ADXL372_POWER_CTL,
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ADXL372_POWER_CTL_MODE_MSK,
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ADXL372_POWER_CTL_MODE(op_mode));
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if (ret < 0)
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return ret;
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st->op_mode = op_mode;
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return ret;
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}
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static int adxl372_set_odr(struct adxl372_state *st,
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enum adxl372_odr odr)
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{
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int ret;
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ret = regmap_update_bits(st->regmap, ADXL372_TIMING,
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ADXL372_TIMING_ODR_MSK,
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ADXL372_TIMING_ODR_MODE(odr));
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if (ret < 0)
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return ret;
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st->odr = odr;
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return ret;
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}
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static int adxl372_set_bandwidth(struct adxl372_state *st,
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enum adxl372_bandwidth bw)
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{
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int ret;
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ret = regmap_update_bits(st->regmap, ADXL372_MEASURE,
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ADXL372_MEASURE_BANDWIDTH_MSK,
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ADXL372_MEASURE_BANDWIDTH_MODE(bw));
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if (ret < 0)
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return ret;
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st->bw = bw;
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return ret;
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}
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static int adxl372_set_act_proc_mode(struct adxl372_state *st,
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enum adxl372_act_proc_mode mode)
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{
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int ret;
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ret = regmap_update_bits(st->regmap,
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ADXL372_MEASURE,
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ADXL372_MEASURE_LINKLOOP_MSK,
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ADXL372_MEASURE_LINKLOOP_MODE(mode));
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if (ret < 0)
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return ret;
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st->act_proc_mode = mode;
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return ret;
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}
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static int adxl372_set_activity_threshold(struct adxl372_state *st,
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enum adxl372_th_activity act,
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bool ref_en, bool enable,
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unsigned int threshold)
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{
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unsigned char buf[6];
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unsigned char th_reg_high_val, th_reg_low_val, th_reg_high_addr;
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/* scale factor is 100 mg/code */
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th_reg_high_val = (threshold / 100) >> 3;
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th_reg_low_val = ((threshold / 100) << 5) | (ref_en << 1) | enable;
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th_reg_high_addr = adxl372_th_reg_high_addr[act];
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buf[0] = th_reg_high_val;
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buf[1] = th_reg_low_val;
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buf[2] = th_reg_high_val;
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buf[3] = th_reg_low_val;
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buf[4] = th_reg_high_val;
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buf[5] = th_reg_low_val;
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return regmap_bulk_write(st->regmap, th_reg_high_addr,
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buf, ARRAY_SIZE(buf));
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}
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static int adxl372_set_activity_time_ms(struct adxl372_state *st,
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unsigned int act_time_ms)
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{
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unsigned int reg_val, scale_factor;
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int ret;
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/*
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* 3.3 ms per code is the scale factor of the TIME_ACT register for
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* ODR = 6400 Hz. It is 6.6 ms per code for ODR = 3200 Hz and below.
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*/
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if (st->odr == ADXL372_ODR_6400HZ)
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scale_factor = 3300;
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else
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scale_factor = 6600;
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reg_val = DIV_ROUND_CLOSEST(act_time_ms * 1000, scale_factor);
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/* TIME_ACT register is 8 bits wide */
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if (reg_val > 0xFF)
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reg_val = 0xFF;
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ret = regmap_write(st->regmap, ADXL372_TIME_ACT, reg_val);
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if (ret < 0)
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return ret;
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st->act_time_ms = act_time_ms;
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return ret;
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}
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static int adxl372_set_inactivity_time_ms(struct adxl372_state *st,
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unsigned int inact_time_ms)
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{
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unsigned int reg_val_h, reg_val_l, res, scale_factor;
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int ret;
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/*
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* 13 ms per code is the scale factor of the TIME_INACT register for
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* ODR = 6400 Hz. It is 26 ms per code for ODR = 3200 Hz and below.
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*/
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if (st->odr == ADXL372_ODR_6400HZ)
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scale_factor = 13;
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else
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scale_factor = 26;
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res = DIV_ROUND_CLOSEST(inact_time_ms, scale_factor);
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reg_val_h = (res >> 8) & 0xFF;
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reg_val_l = res & 0xFF;
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ret = regmap_write(st->regmap, ADXL372_TIME_INACT_H, reg_val_h);
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if (ret < 0)
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return ret;
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ret = regmap_write(st->regmap, ADXL372_TIME_INACT_L, reg_val_l);
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if (ret < 0)
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return ret;
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st->inact_time_ms = inact_time_ms;
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return ret;
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}
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static int adxl372_setup(struct adxl372_state *st)
|
||||
{
|
||||
unsigned int regval;
|
||||
int ret;
|
||||
|
||||
ret = regmap_read(st->regmap, ADXL372_DEVID, ®val);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
if (regval != ADXL372_DEVID_VAL) {
|
||||
dev_err(&st->spi->dev, "Invalid chip id %x\n", regval);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ret = adxl372_set_op_mode(st, ADXL372_STANDBY);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* Set threshold for activity detection to 1g */
|
||||
ret = adxl372_set_activity_threshold(st, ADXL372_ACTIVITY,
|
||||
true, true, 1000);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* Set threshold for inactivity detection to 100mg */
|
||||
ret = adxl372_set_activity_threshold(st, ADXL372_INACTIVITY,
|
||||
true, true, 100);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* Set activity processing in Looped mode */
|
||||
ret = adxl372_set_act_proc_mode(st, ADXL372_LOOPED);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = adxl372_set_odr(st, ADXL372_ODR_6400HZ);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = adxl372_set_bandwidth(st, ADXL372_BW_3200HZ);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* Set activity timer to 1ms */
|
||||
ret = adxl372_set_activity_time_ms(st, 1);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* Set inactivity timer to 10s */
|
||||
ret = adxl372_set_inactivity_time_ms(st, 10000);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* Set the mode of operation to full bandwidth measurement mode */
|
||||
return adxl372_set_op_mode(st, ADXL372_FULL_BW_MEASUREMENT);
|
||||
}
|
||||
|
||||
static int adxl372_reg_access(struct iio_dev *indio_dev,
|
||||
unsigned int reg,
|
||||
unsigned int writeval,
|
||||
unsigned int *readval)
|
||||
{
|
||||
struct adxl372_state *st = iio_priv(indio_dev);
|
||||
|
||||
if (readval)
|
||||
return regmap_read(st->regmap, reg, readval);
|
||||
else
|
||||
return regmap_write(st->regmap, reg, writeval);
|
||||
}
|
||||
|
||||
static int adxl372_read_raw(struct iio_dev *indio_dev,
|
||||
struct iio_chan_spec const *chan,
|
||||
int *val, int *val2, long info)
|
||||
{
|
||||
struct adxl372_state *st = iio_priv(indio_dev);
|
||||
int ret;
|
||||
|
||||
switch (info) {
|
||||
case IIO_CHAN_INFO_RAW:
|
||||
ret = adxl372_read_axis(st, chan->address);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
*val = sign_extend32(ret >> chan->scan_type.shift,
|
||||
chan->scan_type.realbits - 1);
|
||||
return IIO_VAL_INT;
|
||||
case IIO_CHAN_INFO_SCALE:
|
||||
*val = 0;
|
||||
*val2 = ADXL372_USCALE;
|
||||
return IIO_VAL_INT_PLUS_MICRO;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct iio_info adxl372_info = {
|
||||
.read_raw = adxl372_read_raw,
|
||||
.debugfs_reg_access = &adxl372_reg_access,
|
||||
};
|
||||
|
||||
static const struct regmap_config adxl372_spi_regmap_config = {
|
||||
.reg_bits = 7,
|
||||
.pad_bits = 1,
|
||||
.val_bits = 8,
|
||||
.read_flag_mask = BIT(0),
|
||||
};
|
||||
|
||||
static int adxl372_probe(struct spi_device *spi)
|
||||
{
|
||||
struct iio_dev *indio_dev;
|
||||
struct adxl372_state *st;
|
||||
struct regmap *regmap;
|
||||
int ret;
|
||||
|
||||
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
|
||||
if (!indio_dev)
|
||||
return -ENOMEM;
|
||||
|
||||
st = iio_priv(indio_dev);
|
||||
spi_set_drvdata(spi, indio_dev);
|
||||
|
||||
st->spi = spi;
|
||||
|
||||
regmap = devm_regmap_init_spi(spi, &adxl372_spi_regmap_config);
|
||||
if (IS_ERR(regmap))
|
||||
return PTR_ERR(regmap);
|
||||
|
||||
st->regmap = regmap;
|
||||
|
||||
indio_dev->channels = adxl372_channels;
|
||||
indio_dev->num_channels = ARRAY_SIZE(adxl372_channels);
|
||||
indio_dev->dev.parent = &spi->dev;
|
||||
indio_dev->name = spi_get_device_id(spi)->name;
|
||||
indio_dev->info = &adxl372_info;
|
||||
indio_dev->modes = INDIO_DIRECT_MODE;
|
||||
|
||||
ret = adxl372_setup(st);
|
||||
if (ret < 0) {
|
||||
dev_err(&st->spi->dev, "ADXL372 setup failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return devm_iio_device_register(&st->spi->dev, indio_dev);
|
||||
}
|
||||
|
||||
static const struct spi_device_id adxl372_id[] = {
|
||||
{ "adxl372", 0 },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(spi, adxl372_id);
|
||||
|
||||
static struct spi_driver adxl372_driver = {
|
||||
.driver = {
|
||||
.name = KBUILD_MODNAME,
|
||||
},
|
||||
.probe = adxl372_probe,
|
||||
.id_table = adxl372_id,
|
||||
};
|
||||
|
||||
module_spi_driver(adxl372_driver);
|
||||
|
||||
MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
|
||||
MODULE_DESCRIPTION("Analog Devices ADXL372 3-axis accelerometer driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue