ARM: tegra: Enable eDP for Venice2

Venice2 has a 12.9" (2560x1700) panel connected to the eDP output of the
Tegra124. The panel has an EDID to describe the video timings but needs
a few extra nodes to get the backlight to come up.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Thierry Reding 2014-02-28 17:40:24 +01:00 committed by Stephen Warren
parent d72be031b3
commit 40e231c770
1 changed files with 32 additions and 0 deletions

View File

@ -16,6 +16,20 @@ memory {
reg = <0x80000000 0x80000000>;
};
host1x@50000000 {
sor@54540000 {
status = "okay";
nvidia,dpaux = <&dpaux>;
nvidia,panel = <&panel>;
};
dpaux: dpaux@545c0000 {
vdd-supply = <&vdd_3v3_panel>;
status = "okay";
};
};
pinmux: pinmux@70000868 {
pinctrl-names = "default";
pinctrl-0 = <&pinmux_default>;
@ -940,6 +954,17 @@ i2s@70301100 {
};
};
backlight: backlight {
compatible = "pwm-backlight";
enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
power-supply = <&vdd_led>;
pwms = <&pwm 1 1000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
@ -965,6 +990,13 @@ power {
};
};
panel: panel {
compatible = "lg,lp129qe", "simple-panel";
backlight = <&backlight>;
ddc-i2c-bus = <&dpaux>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;