dt-bindings: Add Tegra234 APE support
Add clocks, power-domain and memory bindings to support APE subsystem on Tegra234. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Sameer Pujar
Thierry Reding
parent
38eb21a5fc
commit
40efe139ff
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */
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/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
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#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
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#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
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* @defgroup bpmp_clock_ids Clock ID's
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* @{
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*/
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/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
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#define TEGRA234_CLK_AHUB 4U
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/** @brief output of gate CLK_ENB_APB2APE */
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#define TEGRA234_CLK_APB2APE 5U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
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#define TEGRA234_CLK_APE 6U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
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#define TEGRA234_CLK_AUD_MCLK 7U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
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#define TEGRA234_CLK_DMIC1 15U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */
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#define TEGRA234_CLK_DMIC2 16U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */
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#define TEGRA234_CLK_DMIC3 17U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */
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#define TEGRA234_CLK_DMIC4 18U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */
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#define TEGRA234_CLK_DSPK1 29U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */
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#define TEGRA234_CLK_DSPK2 30U
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/**
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* @brief controls the EMC clock frequency.
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* @details Doing a clk_set_rate on this clock will select the
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#define TEGRA234_CLK_I2C8 54U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
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#define TEGRA234_CLK_I2C9 55U
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/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */
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#define TEGRA234_CLK_I2S1 56U
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/** @brief clock recovered from I2S1 input */
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#define TEGRA234_CLK_I2S1_SYNC_INPUT 57U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
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#define TEGRA234_CLK_I2S2 58U
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/** @brief clock recovered from I2S2 input */
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#define TEGRA234_CLK_I2S2_SYNC_INPUT 59U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
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#define TEGRA234_CLK_I2S3 60U
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/** @brief clock recovered from I2S3 input */
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#define TEGRA234_CLK_I2S3_SYNC_INPUT 61U
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/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */
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#define TEGRA234_CLK_I2S4 62U
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/** @brief clock recovered from I2S4 input */
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#define TEGRA234_CLK_I2S4_SYNC_INPUT 63U
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/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */
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#define TEGRA234_CLK_I2S5 64U
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/** @brief clock recovered from I2S5 input */
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#define TEGRA234_CLK_I2S5_SYNC_INPUT 65U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S6 */
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#define TEGRA234_CLK_I2S6 66U
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/** @brief clock recovered from I2S6 input */
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#define TEGRA234_CLK_I2S6_SYNC_INPUT 67U
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/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
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#define TEGRA234_CLK_PLLA 93U
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/** @brief PLLP clk output */
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#define TEGRA234_CLK_PLLP_OUT0 102U
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/** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */
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#define TEGRA234_CLK_PLLA_OUT0 104U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
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#define TEGRA234_CLK_PWM1 105U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
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#define TEGRA234_CLK_PWM8 112U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
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#define TEGRA234_CLK_SDMMC4 123U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */
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#define TEGRA234_CLK_SYNC_DMIC1 139U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */
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#define TEGRA234_CLK_SYNC_DMIC2 140U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */
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#define TEGRA234_CLK_SYNC_DMIC3 141U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */
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#define TEGRA234_CLK_SYNC_DMIC4 142U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */
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#define TEGRA234_CLK_SYNC_DSPK1 143U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */
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#define TEGRA234_CLK_SYNC_DSPK2 144U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */
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#define TEGRA234_CLK_SYNC_I2S1 145U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */
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#define TEGRA234_CLK_SYNC_I2S2 146U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */
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#define TEGRA234_CLK_SYNC_I2S3 147U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */
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#define TEGRA234_CLK_SYNC_I2S4 148U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */
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#define TEGRA234_CLK_SYNC_I2S5 149U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */
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#define TEGRA234_CLK_SYNC_I2S6 150U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
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#define TEGRA234_CLK_UARTA 155U
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
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#ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H
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#define DT_BINDINGS_MEMORY_TEGRA234_MC_H
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#define TEGRA234_SID_INVALID 0x00
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#define TEGRA234_SID_PASSTHROUGH 0x7f
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/* NISO0 stream IDs */
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#define TEGRA234_SID_APE 0x02
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/* NISO1 stream IDs */
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#define TEGRA234_SID_SDMMC4 0x02
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#define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95
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/* BPMPDMA write client */
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#define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96
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/* APEDMA read client */
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#define TEGRA234_MEMORY_CLIENT_APEDMAR 0x9f
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/* APEDMA write client */
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#define TEGRA234_MEMORY_CLIENT_APEDMAW 0xa0
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#endif
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
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#ifndef __ABI_MACH_T234_POWERGATE_T234_H_
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#define __ABI_MACH_T234_POWERGATE_T234_H_
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#define TEGRA234_POWER_DOMAIN_AUD 2U
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#endif
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