dma-mapping: remove arch_dma_mmap_pgprot
arch_dma_mmap_pgprot is used for two things: 1) to override the "normal" uncached page attributes for mapping memory coherent to devices that can't snoop the CPU caches 2) to provide the special DMA_ATTR_WRITE_COMBINE semantics on older arm systems and some mips platforms Replace one with the pgprot_dmacoherent macro that is already provided by arm and much simpler to use, and lift the DMA_ATTR_WRITE_COMBINE handling to common code with an explicit arch opt-in. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> # m68k Acked-by: Paul Burton <paul.burton@mips.com> # mips
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@ -8,7 +8,7 @@ config ARM
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select ARCH_HAS_DEBUG_VIRTUAL if MMU
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select ARCH_HAS_DEVMEM_IS_ALLOWED
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select ARCH_HAS_DMA_COHERENT_TO_PFN if SWIOTLB
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select ARCH_HAS_DMA_MMAP_PGPROT if SWIOTLB
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select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
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select ARCH_HAS_ELF_RANDOMIZE
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select ARCH_HAS_FORTIFY_SOURCE
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select ARCH_HAS_KEEPINITRD
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@ -2402,12 +2402,6 @@ long arch_dma_coherent_to_pfn(struct device *dev, void *cpu_addr,
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return dma_to_pfn(dev, dma_addr);
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}
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pgprot_t arch_dma_mmap_pgprot(struct device *dev, pgprot_t prot,
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unsigned long attrs)
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{
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return __get_dma_pgprot(attrs, prot);
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}
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void *arch_dma_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle,
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gfp_t gfp, unsigned long attrs)
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{
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@ -13,7 +13,6 @@ config ARM64
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select ARCH_HAS_DEBUG_VIRTUAL
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select ARCH_HAS_DEVMEM_IS_ALLOWED
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select ARCH_HAS_DMA_COHERENT_TO_PFN
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select ARCH_HAS_DMA_MMAP_PGPROT
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select ARCH_HAS_DMA_PREP_COHERENT
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select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
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select ARCH_HAS_ELF_RANDOMIZE
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@ -435,6 +435,10 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd)
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__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
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#define pgprot_device(prot) \
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__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
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#define pgprot_dmacoherent(prot) \
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__pgprot_modify(prot, PTE_ATTRINDX_MASK, \
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PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
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#define __HAVE_PHYS_MEM_ACCESS_PROT
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struct file;
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extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
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@ -11,12 +11,6 @@
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#include <asm/cacheflush.h>
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pgprot_t arch_dma_mmap_pgprot(struct device *dev, pgprot_t prot,
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unsigned long attrs)
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{
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return pgprot_writecombine(prot);
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}
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void arch_sync_dma_for_device(struct device *dev, phys_addr_t paddr,
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size_t size, enum dma_data_direction dir)
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{
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@ -4,7 +4,6 @@ config M68K
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default y
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select ARCH_32BIT_OFF_T
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select ARCH_HAS_BINFMT_FLAT
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select ARCH_HAS_DMA_MMAP_PGPROT if MMU && !COLDFIRE
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select ARCH_HAS_DMA_PREP_COHERENT if HAS_DMA && MMU && !COLDFIRE
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select ARCH_HAS_SYNC_DMA_FOR_DEVICE if HAS_DMA
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select ARCH_MIGHT_HAVE_PC_PARPORT if ISA
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@ -169,6 +169,9 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
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? (__pgprot((pgprot_val(prot) & _CACHEMASK040) | _PAGE_NOCACHE_S)) \
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: (prot)))
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pgprot_t pgprot_dmacoherent(pgprot_t prot);
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#define pgprot_dmacoherent(prot) pgprot_dmacoherent(prot)
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#endif /* CONFIG_COLDFIRE */
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#include <asm-generic/pgtable.h>
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#endif /* !__ASSEMBLY__ */
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@ -23,8 +23,7 @@ void arch_dma_prep_coherent(struct page *page, size_t size)
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cache_push(page_to_phys(page), size);
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}
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pgprot_t arch_dma_mmap_pgprot(struct device *dev, pgprot_t prot,
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unsigned long attrs)
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pgprot_t pgprot_dmacoherent(pgprot_t prot)
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{
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if (CPU_IS_040_OR_060) {
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pgprot_val(prot) &= ~_PAGE_CACHE040;
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@ -1119,7 +1119,7 @@ config DMA_PERDEV_COHERENT
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config DMA_NONCOHERENT
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bool
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select ARCH_HAS_DMA_MMAP_PGPROT
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select ARCH_HAS_DMA_WRITE_COMBINE
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select ARCH_HAS_SYNC_DMA_FOR_DEVICE
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select ARCH_HAS_UNCACHED_SEGMENT
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select NEED_DMA_MAP_STATE
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@ -65,14 +65,6 @@ long arch_dma_coherent_to_pfn(struct device *dev, void *cpu_addr,
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return page_to_pfn(virt_to_page(cached_kernel_address(cpu_addr)));
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}
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pgprot_t arch_dma_mmap_pgprot(struct device *dev, pgprot_t prot,
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unsigned long attrs)
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{
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if (attrs & DMA_ATTR_WRITE_COMBINE)
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return pgprot_writecombine(prot);
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return pgprot_noncached(prot);
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}
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static inline void dma_sync_virt(void *addr, size_t size,
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enum dma_data_direction dir)
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{
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@ -3,6 +3,7 @@
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#define _LINUX_DMA_NONCOHERENT_H 1
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#include <linux/dma-mapping.h>
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#include <asm/pgtable.h>
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#ifdef CONFIG_ARCH_HAS_DMA_COHERENCE_H
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#include <asm/dma-coherence.h>
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@ -42,10 +43,18 @@ void arch_dma_free(struct device *dev, size_t size, void *cpu_addr,
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dma_addr_t dma_addr, unsigned long attrs);
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long arch_dma_coherent_to_pfn(struct device *dev, void *cpu_addr,
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dma_addr_t dma_addr);
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pgprot_t arch_dma_mmap_pgprot(struct device *dev, pgprot_t prot,
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unsigned long attrs);
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#ifdef CONFIG_MMU
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/*
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* Page protection so that devices that can't snoop CPU caches can use the
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* memory coherently. We default to pgprot_noncached which is usually used
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* for ioremap as a safe bet, but architectures can override this with less
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* strict semantics if possible.
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*/
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#ifndef pgprot_dmacoherent
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#define pgprot_dmacoherent(prot) pgprot_noncached(prot)
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#endif
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pgprot_t dma_pgprot(struct device *dev, pgprot_t prot, unsigned long attrs);
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#else
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static inline pgprot_t dma_pgprot(struct device *dev, pgprot_t prot,
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@ -20,6 +20,15 @@ config ARCH_HAS_DMA_COHERENCE_H
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config ARCH_HAS_DMA_SET_MASK
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bool
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#
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# Select this option if the architecture needs special handling for
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# DMA_ATTR_WRITE_COMBINE. Normally the "uncached" mapping should be what
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# people thing of when saying write combine, so very few platforms should
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# need to enable this.
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#
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config ARCH_HAS_DMA_WRITE_COMBINE
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bool
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config DMA_DECLARE_COHERENT
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bool
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@ -45,9 +54,6 @@ config ARCH_HAS_DMA_PREP_COHERENT
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config ARCH_HAS_DMA_COHERENT_TO_PFN
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bool
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config ARCH_HAS_DMA_MMAP_PGPROT
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bool
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config ARCH_HAS_FORCE_DMA_UNENCRYPTED
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bool
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@ -161,9 +161,11 @@ pgprot_t dma_pgprot(struct device *dev, pgprot_t prot, unsigned long attrs)
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(IS_ENABLED(CONFIG_DMA_NONCOHERENT_CACHE_SYNC) &&
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(attrs & DMA_ATTR_NON_CONSISTENT)))
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return prot;
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if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_MMAP_PGPROT))
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return arch_dma_mmap_pgprot(dev, prot, attrs);
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return pgprot_noncached(prot);
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#ifdef CONFIG_ARCH_HAS_DMA_WRITE_COMBINE
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if (attrs & DMA_ATTR_WRITE_COMBINE)
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return pgprot_writecombine(prot);
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#endif
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return pgprot_dmacoherent(prot);
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}
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#endif /* CONFIG_MMU */
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